A power semiconductor chip gate region

Abstract

The invention provides a gate region of a power semiconductor chip, which comprises a main gate region, a first grid strip and a gate resistance region, wherein the main gate region is positioned in a chip cellular area; the first grid strip surrounds the main gate region; the gate resistance area is positioned between the main gate region and the first grid strip; at least two sub-resistances are connected in parallel in the gate resistance area; one end of each sub-resistance is connected with the main gate region; the other end of each sub-resistance is connected with the first grid strip. The gate region structure avoids the risk that the entire chip can not work normally or is damaged due to damage of one gate resistance. In addition, the structure that a plurality of resistances are connected in parallel is adopted to greatly reduce huge changes of resistance value of the resistance due to the error of the gate resistance, so that uniformity of the switching speed between two chips and the uniform current distribution property between two chips are ensured.

Description

technical field [0001] The invention relates to the field of semiconductor devices, in particular to a gate region of a power semiconductor chip. Background technique [0002] At present, the gate region structure of power semiconductor chips such as IGBT, MOSFET, etc. in the prior art includes two parts, the gate pad region and the gate bus bar, wherein the gate pad region and the gate bus bar are electrically connected through a series resistor. The structure of the gate region has the following disadvantages: [0003] First, when the resistance connected in series between the gate pad area and the gate bus bar is damaged, the gate pad area and the bus bar cannot be connected, which affects the normal operation of the chip and even causes damage to the chip. [0004] Secondly, in many application fields of power electronic devices, multiple power semiconductor chips are often connected in parallel to achieve the target power level. The multiple power semiconductor chips ...

AI Technical Summary

Problems solved by technology

Since the error of the resistance value of a single resistor is generally large, for the same gate pad area signal between different chips, the signal on the gate bus bar is very different, which easily leads to uneven switching speed and uneven current technology between chips. question

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