Stacked Package Devices
A technology for packaging devices and packaging components, which is applied in the manufacturing of electrical solid-state devices, semiconductor devices, and semiconductor/solid-state devices. It can solve problems such as thickness and thickness, and achieve the effect of reducing thickness and size.
Active Publication Date: 2016-06-15
SHENZHEN SIPTORY TECH CO LTD
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Problems solved by technology
[0003] However, the multi-layer stacked package devices in the prior art usually have a relatively thick thickness, especially when the number of stacked layers exceeds 3 layers, the situation of its thicker thickness is more serious
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[0016] The present invention will be described in detail below in conjunction with the drawings.
[0017] The detailed description of the present invention directly or indirectly simulates the operation of the technical solution of the present invention through programs, steps, logic blocks, processes or other symbolic descriptions. For a thorough understanding of the present invention, many specific details are stated in the following description. Without these specific details, the present invention may still be implemented. Those skilled in the field use these descriptions and statements here to effectively introduce the nature of their work to other technical personnel in the field. In other words, in order to avoid obscuring the purpose of the present invention, since the well-known methods and procedures have been easily understood, they have not been described in detail.
[0018] The "one embodiment" or "embodiment" referred to herein refers to a specific feature, structur...
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The invention discloses a stack packaging device. The device comprises a first packaging component, a second packaging component, a plurality of first interconnection components and a plurality of second interconnection components. The first packaging component comprises a first substrate and a first semiconductor wafer installed on a first surface of the first substrate. The second packaging component comprises a second substrate and a second semiconductor wafer installed on a second surface of the second substrate. One end of each first interconnection component is connected with a second surface of the first substrate and the other end is connected with the first surface of the second substrate. A third packaging component comprises a third substrate and a third semiconductor wafer installed on the first surface of the third substrate. The one end of each second interconnection component is connected with the second surface of the first substrate or the first surface of the second substrate and the other end is connected with the first surface of the third substrate. The structure fully uses a gap between the first packaging component and the second packaging component so that a thickness of the multilayer stack packaging device is reduced as a whole.
Description
Technical field [0001] The present invention relates to the field of semiconductor packaging, in particular to a high-density multi-layer stacked package (Package on package, POP for short) device. Background technique [0002] As the size of electronic devices is reduced, high integration density can be achieved by stacking multiple chips in one semiconductor package or stacking multiple individual semiconductor packages. Recently, stacked semiconductor packages have been introduced for mobile electronic device applications and the like. One of the stacked semiconductor packages is a package on package (POP) in which a logic package device and a memory package device are stacked. Using POP technology, different types of semiconductor chips can be included in one semiconductor package. [0003] However, the multi-layer stacked package device in the prior art usually has a thicker thickness, especially when the number of stacked layers exceeds 3 layers, the thicker thickness is mo...
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IPC IPC(8): H01L23/488H01L21/60
CPCH01L2224/48091H01L2224/73265
Inventor 王宏杰陆原孙鹏黄卫东耿菲
Owner SHENZHEN SIPTORY TECH CO LTD