How to form a mos transistor

Abstract

A forming method of an MOS transistor comprises the steps that a semiconductor substrate is provided, wherein the semiconductor substrate comprises a first region and a second region, a first grid structure of a PMOS transistor is formed on the surface, in the first region, of the semiconductor substrate, and a second grid structure of an NMOS transistor is formed on the surface, in the second region, of the semiconductor substrate; first grooves are formed in positions, on the two sides of the first grid structure of the first region, in the semiconductor substrate, and second grooves are formed in positions, on the two sides of the second grid structure of the second region, in the semiconductor substrate; the first grooves and the second grooves are filled with silicon-germanium layers; ion implantation is conducted on the silicon-germanium layers in the second grooves, and stress of the silicon-germanium layers in the second grooves is released. The forming method of the MOS transistor is simple in technology step.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a method for forming a MOS transistor. Background technique [0002] In the existing manufacturing process of semiconductor devices, since stress can change the energy gap and carrier mobility of silicon materials, it has become an increasingly common means to improve the performance of MOS transistors through stress. Specifically, by properly controlling the stress, the mobility of carriers (electrons in NMOS transistors and holes in PMOS transistors) can be increased, thereby increasing the driving current, thereby greatly improving the performance of MOS transistors. [0003] At present, embedded silicon germanium (Embedded SiGe) technology is used to improve the mobility of holes in the channel region of PMOS transistors, that is, silicon germanium materials are first formed in the regions where source and drain regions need to be formed, and then doped to form PMOS...

AI Technical Summary

Problems solved by technology

[0009] The current process steps of forming a silicon germanium layer in the PMOS source / drain region using an integrated process are relatively complicated

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