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Data rearrangement method and device

A technology for data and group data, applied in the field of data rearrangement methods and devices, can solve the problems of increased consumption of ping-pong cache, waste of cache, large amount of RAM, etc.

Inactive Publication Date: 2013-11-13
POTEVIO INFORMATION TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Usually, when the length of the basic data unit is short, it is a feasible method to use the ping-pong cache to realize data rearrangement. The additional RAM consumed by the ping-pong cache is relatively small. As the length of the basic data unit increases, when the When the data is full, the remaining storage space is not enough to store a complete basic data unit, so the remaining storage space can only be empty, and the cost of the ping-pong cache will increase greatly. When the length of the basic data unit is long, the ping-pong cache will be extra The amount of RAM consumed will be large, which is a big waste of cache

Method used

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Examples

Experimental program
Comparison scheme
Effect test

example 1

[0065] Example 1: The input format of the input data X(n) is:

[0066] A 0 A 1 …………A m-2 A m-1

[0067] ................................................

[0068] A m A m+1 …………A 2m-2 A 2m-1

[0069] ................................................

[0070] A 2m A 2m+1 …………A 3m-2 A 3m-1

[0071] ...................................,

[0072] The format of the read data Y(n) is:

[0073] A m-1 A m-2 …………A 1 A 0

[0074] ................................................

[0075] A 2m-1 A 2m-2 …………A m+1 A m

[0076] ................................................

[0077] A 3m-1 A 3m-2 …………A 2m+1 A 2m

[0078] ................................................

[0079] RAM cache example when;

[0080] (1) According to the format of input and output data, open up a buffer RAM space in FPGA, and the depth of RAM is equal to the minimum buffer size, that is, m.

[0081](2) Group the serially input data X(n) into groups, the group number starts from nu...

example 2

[0084] Example 2: The input format of the input data X(n) is:

[0085] A 0 A 1 …………A m-2 A m-1

[0086] B 0 B 1 …………B m-2 B m-1

[0087] C 0 C 1 …………C m-2 C m-1

[0088] D. 0 D. 1 …………D m-2 D. m-1

[0089] E. 0 E. 1 ………E m-2 E. m-1

[0090] f 0 f 1 ………F m-2 f m-1

[0091] G 0 G 1 ………… G m-2 G m-1

[0092] h 0 h 1 ………H m-2 h m-1

[0093] A m A m+1 …………A 2m-2 A 2m-1 ,

[0094] ...................................,

[0095] The format of the read data Y(n) is:

[0096] A 0 B 0 C 0 D. 0 E. 0 f 0 G 0 h 0

[0097] A 1 B 1 C 1 D. 1 E. 1 f 1 G 1 h 1

[0098] ...................................

[0099] A m-2 B m-2 C m-2 D. m-2 E. m-2 f m-2 G m-2 h m-2

[0100] A m-1 B m-1 C m-1 D. m-1 E. m-1 f m-1 G m-1 h m-1

[0101] A m B m C m D. m E. m f m G m h m

[0102] ...................................

[0103] A 2m-1 B 2m-1 C 2m-1 D. 2m-1 E. 2m-1 f 2m-1 G 2m-1 h 2m-1

[0104] ....................

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Abstract

The invention provides a data rearrangement device which comprises a forestage processing module, a caching module, a backward-stage processing module and an address control module and also comprises a write address conversion module and a read address conversion module. Compared with a ping-pong cache in the prior art, the data arrangement device has the advantages that a half of a random access memory (RAM) can be saved, and read-write operation of the RAM is easy to control; a new address can be generated by simple conversion of an actual written address, and the address generation operation is regular; and a structure rule is very suitable for the characteristic of operation flexibility of a field programmable gate array (FPGA).

Description

technical field [0001] The present invention relates to the technical field of mobile communication, in particular to a data rearrangement method and device. Background technique [0002] In the LTE system, it is often encountered a scenario where data needs to be rearranged, that is, multiple data streams are changed from serial to interleaved arrangement, or from interleaved arrangement to serial arrangement. For example, in the baseband processing board, the Fast Fourier Transform (FFT) operation on the data of 8 antennas in a cell is implemented serially, while the data transmission format on the subsequent Ir interface is transmitted interleaved according to the antenna data, so that It is necessary to change the transmission format of the data, and it is necessary to use random access memory (RAM, random access memory) in the Field Programmable Gate Array (FPGA) for caching. [0003] The data rearrangement process in the prior art is as follows: First, write the data ...

Claims

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Application Information

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IPC IPC(8): G06F12/08G06F12/10G06F12/0862G06F12/1081
Inventor 吴恂李朝峰张慧欣
Owner POTEVIO INFORMATION TECH