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Method and apparatus for reducing erase disturb in memory by using reset bias

A technology of storage unit and volatile storage, applied in the field of memory

Active Publication Date: 2016-04-13
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the erase algorithm does not correct for erase disturbances in cells not selected for erasure

Method used

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  • Method and apparatus for reducing erase disturb in memory by using reset bias
  • Method and apparatus for reducing erase disturb in memory by using reset bias
  • Method and apparatus for reducing erase disturb in memory by using reset bias

Examples

Experimental program
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Embodiment Construction

[0031] figure 1 An example flowchart showing an erase algorithm with recovery programming for unselected erased memory cells in a memory group.

[0032] In step 10, the integrated circuit with memory array receives an erase command. The wipe command specifies one or more storage groups to be wiped. A memory group may be a group of memory cells such as sectors, blocks, or segments that are to be erased together. The storage unit group can also be the entire storage array.

[0033] The erasure algorithm performs multiple steps on one or more storage groups selected to be erased, and then performs multiple steps on one or more storage groups not selected to be erased. First, a number of steps are performed on one or more storage groups selected to be erased.

[0034] In step 12, pre-programming is performed on all or a subset of the memory cells in the erased state in the selected memory group to be erased. Such preprogramming brings the memory cells in the memory group to a...

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PUM

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Abstract

The invention discloses a method and a device for reducing erase disturbance in memory by using return bias voltage. A non-volatile memory array is divided into a plurality of storage groups; and the non-volatile memory array receives an erase command to erase a first storage group, without erasing a second storage group. The control circuit responses to the erase command and applies a return bias voltage to adjust a threshold voltage of a storage unit of at least one storage group in the second storage group, so as to erase the first storage group. Through applying the return bias voltage on the at least one storage group in the second storage group, the return bias voltage at least can correct part of the erase disturbance.

Description

technical field [0001] The invention relates to the technical field of memory, in particular to a method and a device for reducing erasing interference in memory by using a recovery bias voltage. Background technique [0002] The erase algorithm for non-volatile memory cells is to pre-program erase the memory cells to a programmed state, then erase, and then follow a soft programming of the over-erased memory cells. This pre-programming and soft-programming are additional steps to the erase operation and correct the threshold voltage distribution of the portion of the memory array that is selected for erasing memory cells. However, the erase algorithm does not correct for erase disturbances in memory cells not selected for erasure. Erase disturb refers to the effect that memory cells that are not selected for erasure are also erased to some extent. Contents of the invention [0003] The techniques described herein provide an integrated circuit having a nonvolatile memory...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C16/14G11C16/02
Inventor 洪俊雄吴柏璋张坤龙陈耕晖
Owner MACRONIX INT CO LTD