Method and device for protecting chip top-layer covering integrity

A technology of integrity protection and chips, applied in the direction of internal/peripheral computer component protection, etc., can solve the problems of low security, simple detection mechanism, high power consumption, etc., and achieve the effect of solving low security

Active Publication Date: 2013-11-27
DATANG MICROELECTRONICS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

The existing top-layer metal coverage integrity protection circuit has a simple detection mechanism, low security, and high power consumption. In addition, in the prior art, a group of m metal input terminals changes at the same time, and the resistance value of the top-layer metal is small. The circuit flips in an instant, which will cause a sharp increase in the power consumption of the chip in an instant

Method used

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  • Method and device for protecting chip top-layer covering integrity
  • Method and device for protecting chip top-layer covering integrity
  • Method and device for protecting chip top-layer covering integrity

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Embodiment

[0096] In the embodiment of the present invention, the top layer metal is divided into n groups, and each group has 8 metal lines, that is, M=8. After the system is reset, the initial value of each group of metal lines ([7:0]) is all "0". When the work enable signal is valid (en="1"), the circuit enters the work mode, and starts to detect whether the metal on the top layer of the entire chip is abnormal, and supports cycle detection.

[0097] The top metal wire covers the entire chip. When the chip is attacked by the top layer "stripping", whether only one or more metal wires on the top layer are cut, or the entire top layer is cut, an abnormal alarm interrupt can be generated. Figure 4 As shown, the second dashed line that is not connected represents a metal line that has been cut:

[0098] Detection order: check the first group, the second group of connections sequentially, and so on, and finally check the nth group.

[0099] When detecting a certain group, store the pre-...

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Abstract

The invention discloses a method and a device for protecting chip top-layer covering integrity, and relates to the field of chip physical integrity protection. The method is applied to a physical layer protecting circuit, the physical layer protecting circuit is divided into n groups, and each group has M metal wires. In each detection cycle, the method includes A, generating random binary numbers with at least M bits; B, inputting the random binary numbers into the input ends of the M metal wires in each group; C, detecting output signals of the M metal wires, and if the output signals are not identical to the random binary numbers inputted into the M metal wires, determining that a chip is attacked. The device comprises a random number generator, a controller and a detection side. Chip top-layer metal covering integrity protection of the method and the device is based on a random number comparison method, and compared with the prior art, the method and the device have the advantages that the technical defects of low safety and high power consumption are overcome.

Description

technical field [0001] The invention relates to the field of chip physical integrity protection. Background technique [0002] Metal covering on the top layer of the chip is one of the design methods for high-security smart card chips. By covering the top layer of the chip with a layer of metal medium, the underlying circuits and signals of the chip can be effectively protected from external malicious attacks. However, with the continuous improvement of attack methods in recent years, the top layer of metal is easily stripped by attackers and loses its protective significance. Therefore, a safe and complete top-level metal coverage must simultaneously provide logical protection for the integrity of the metal coverage. [0003] The design principle of the existing top-layer metal coverage integrity logic protection circuit is: add logic gate circuits at both ends of the multiple metal lines covered by the top layer. If the metal is effectively connected, the logic value of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F21/87
Inventor 王震赵红敏
Owner DATANG MICROELECTRONICS TECH CO LTD
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