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Automatic regression method of FPGA (Field Programmable Gate Array) simulation test cases

An automated regression and test case technology, applied in special data processing applications, instruments, electrical digital data processing, etc., can solve problems such as low work efficiency, time-consuming and labor-consuming, and increased times, so as to reduce workload and time, improve The effect of work efficiency

Active Publication Date: 2013-12-18
SHANGHAI BEIJING UNIV FOUNDER TECH COMP SYST
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, to manually execute a test case, you need to enter at least 4 commands on the keyboard. If there are 50 test cases in a project, you need to manually enter 200 commands to complete a regression, and you need to check whether each simulation log is wrong. It is very time-consuming and labor-intensive, and the work efficiency is low
In addition, the current test case development is based on the method of random verification and functional coverage. Using one seed to regress the test case once cannot meet the coverage requirements, so it is necessary to return multiple times with different seeds, so that the manual execution of the test case will multiply

Method used

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  • Automatic regression method of FPGA (Field Programmable Gate Array) simulation test cases

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Embodiment Construction

[0031] The script is written in Perl language. The Perl language has the advantages of simplicity, few restrictions, and high speed. The script consists of the following subroutines:

[0032] is_windows(): Determine whether to run in Windows or Linux environment, so as to use the corresponding operation command.

[0033] check_time(): Record the start and end times of the simulation.

[0034] usage(): Display help information.

[0035] show_case(): Get the test case name from the test case list.

[0036] show_group(): Get a group of test cases from the test case list.

[0037] clean_env(): Delete the previously compiled library files, delete the files generated by the previously compiled design and verification code, and delete the previous logs and waveforms. In order to ensure the correctness of code regression in different versions, it is necessary to delete the locally compiled files before recompiling.

[0038] setup(): Call the command to compile the library file, ...

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Abstract

The invention discloses an automatic regression method of FPGA (Field Programmable Gate Array) simulation test cases. The automatic regression method comprises the steps of 1) selecting a group of test cases from a test case list by an FPGA; 2) deleting library files, compiling files, simulation logs and wave shapes of the selected test cases; 3) compiling a corresponding library file and a compiling file for each selected test case by the FPGA; 4) invoking a simulation tool for running each test case by the FPGA, then searching the test case in the test case list and putting the test case in a corresponding test case group; 5) submitting each test case to a server for carrying out regression or locally carrying out the regression by the FPGA; 6) searching the simulation log of each test case by the FPGA, and generating a test report. According to the automatic regression method disclosed by the invention, a simulation test result of the test cases can be quickly obtained, and thus the working efficiency is greatly increased.

Description

technical field [0001] The invention relates to an automatic regression method for FPGA simulation test cases, belonging to the technical field of computer software. technical background [0002] With the increasing capacity and scale of FPGA, the complexity of FPGA design is getting higher and higher. In order to ensure the quality of design, it is necessary to rely on simulation tools for test verification. Currently commonly used simulation tools include Questasim, VCS, NC-sim, etc., verification languages ​​include systemverilog, systemC, etc., and verification methods include VMM, OVM, UVM, etc. The simulation tool can simulate the behavior of the FPGA design code, and it can be easily debugged through logs and waveforms. The verification language and verification methodology are used to build a verification environment. After compiling and running through the simulation tool, the required stimulus can be generated according to the interface protocol, and the design co...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 蔡潇
Owner SHANGHAI BEIJING UNIV FOUNDER TECH COMP SYST