Data transmission method capable of ensuring small capacity cache serial communication safety
A data transmission method and a technology for buffering serial ports, which are applied in the direction of electrical digital data processing and instruments, can solve the problems of inability to guarantee the continuity of data transmission, increase the complexity and cost of the system, and frequently interrupt the probability, so as to ensure reliability And continuity, easy to implement, strong practical effects
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Embodiment 1
[0041] Taking the cache FIFO capacity as 4 bytes as an example, the data transmission method includes the following steps:
[0042] (1) The host computer initializes the serial port and completes the configuration of the serial port working status, including baud rate setting, parity setting, stop bit number setting, interrupt mode setting (clock) and clearing FIFO.
[0043] (2) The upper computer sends control instructions to the transmission state machine, and the transmission state machine stops data transmission according to the control instructions.
[0044] (3) The host computer writes data into the cache FIFO, and the number of written data is less than or equal to the capacity N of the cache FIFO, and at the same time, the host computer sends a control command to the transmission state machine.
[0045] (4) The transmission state machine reads the data from the buffer FIFO according to the control instruction and transmits it to the shift register, and the shift regist...
Embodiment 2
[0050] Still taking the buffer FIFO capacity as 4 bytes as an example, the data transmission method includes the following steps:
[0051] (1) The host computer initializes the serial port and completes the configuration of the serial port working status, including baud rate setting, parity setting, stop bit number setting, interrupt mode setting (clock) and clearing FIFO.
[0052] (2) The upper computer sends control instructions to the transmission state machine, and the transmission state machine stops data transmission according to the control instructions.
[0053] (3) The host computer writes data into the cache FIFO, and the number of written data is less than or equal to the capacity N of the cache FIFO, and at the same time, the host computer sends a control command to the transmission state machine.
[0054] (4) The transmission state machine reads the data from the buffer FIFO according to the control instruction and transmits it to the shift register, and the shift...
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