Code rate regulation device with resistance to burst big error code
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[0034] The present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.
[0035] Such as figure 1 As shown, a code rate adjustment device for resisting bursty large errors, which is implemented based on FPGA or ASIC, includes a multiframe generator 1, a service flag generator 2, a frequency flag generator 3, a transmission data buffer 4, a data multiplexing module 5, data demultiplexing module 6, frequency controller 7, receiving data buffer 8, figure 1 It is an electric principle block diagram of the present invention, and the embodiment is according to figure 1 Connect the lines. in:
[0036] The multiframe generator 1 is used to provide the multiframe flag generator with the frame flag signal needed for wireless channel multiplexing.
[0037] The data flag generator 2 generates a data adjustment flag within a fixed time according to the received service signal. The flag is the same in each multiframe...
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