Static random access memory and method for improving writing-in redundancy rate of static random access memory

A static random, write redundant technology, applied in semiconductor/solid-state device manufacturing, electric solid-state devices, semiconductor devices, etc., can solve the problems of small equivalent resistance, small write redundancy, etc., to achieve increased equivalent Resistance, improved hole mobility, and improved write redundancy

Active Publication Date: 2014-02-12
SHANGHAI HUALI MICROELECTRONICS CORP
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, in the existing SRAM, the equivalent resistance of the pull-up transistor is small, which in turn leads to a small write margin (Write Margin) of the SRAM

Method used

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  • Static random access memory and method for improving writing-in redundancy rate of static random access memory
  • Static random access memory and method for improving writing-in redundancy rate of static random access memory
  • Static random access memory and method for improving writing-in redundancy rate of static random access memory

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Embodiment Construction

[0024] In order to illustrate the technical content, structural features, achieved goals and effects of the present invention in detail, the following will be described in detail in conjunction with the embodiments and accompanying drawings.

[0025] see figure 1 , figure 1 Shown is a schematic diagram of an equivalent circuit for writing in the SRAM of the present invention. Write margin (Write Margin) is an important parameter to measure the write performance of the SRAM unit. In the writing equivalent circuit of the SRAM, it is assumed that the first node 1 stores data at a low potential (that is, the stored data is "0"), and the second node 2 stores data at a high potential (that is, stores The data is "1"), non-limiting list, for example, writing a high potential to the first node 1, writing a low potential to the second node 2, before the writing action, the first bit line 3 will be precharged to a high potential, and the second bit line 4 will be precharged to a low ...

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Abstract

A static random access memory comprises a silicon-based substrate, a shallow-channel isolator arranged in the silicon-based substrate, an NMOS device, a PMOS device and an upwards-pull transistor. Silicon-germanium lattice structures are arranged in a source electrode area and a drain electrode area of the PMOS device. The upwards-pull transistor is a PMOS, and no silicon-germanium lattice structure is arranged in a source electrode area and a drain electrode area of the upwards-pull transistor. As the silicon-germanium lattice structures are arranged in the source electrode area and the drain electrode area of the PMOS device, pressure stress in a channel of the PMOS device is increased, and then the effect of improving the hole mobility of the PMOS device is improved. As no silicon-germanium lattice structure is arranged in the source electrode area and the drain electrode area of the upwards-pull transistor, pressure stress in the channel direction of the upwards-pull transistor is decreased, the carrier mobility of the upwards-pull transistor is reduced, the equivalent resistance of the upwards-pull transistor is increased, and then the writing-in redundancy rate of the static random access memory is improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a static random access memory and a method for improving write redundancy thereof. Background technique [0002] Static Random Access Memory (SRAM), as an important product in semiconductor memory, has been widely used in high-speed data exchange systems such as computers, communications, and multimedia. [0003] Generally, the layout of the SRAM below 90nm includes three levels of active area, polysilicon gate, and contact holes, and control transistors are respectively formed on the layout area, and the control transistors are NMOS devices; pull-down transistors (Pull Down MOS), the pull-down transistor is an NMOS device; the pull-up transistor (Pull Up MOS), the pull-up transistor is a PMOS device. However, in the existing SRAM, the equivalent resistance of the pull-up transistor is small, which leads to a small write margin (Write Margin) of the SRAM. Seeking a metho...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/11H01L29/06H01L21/8244
Inventor 俞柳江
Owner SHANGHAI HUALI MICROELECTRONICS CORP
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