Error correcting write-back method for SRAM (Static Random Access Memory)

Abstract

The invention provides an error correcting write-back method for an SRAM (Static Random Access Memory). The error correcting write-back method is used for solving technical problems. According to the method, error correcting control signals are generated through redundancy check bits, and the generation of write-back write-in signals and write-back address signals is controlled by the error correcting control signals, so that the invariance of the address signals is ensured; data stored in an n-bit storage unit are promptly written in the SRAM so as to complete a write-back function, then, the condition that the data are not damaged and are written back according to an original address is ensured, the condition that original data are not damaged after the data are read is guaranteed, and cumulative errors are avoided.

Description

technical field [0001] The invention relates to a method for reliability of SRAM data, in particular to a method for preventing original data from being damaged when the SRAM data storage structure is read and written. Background technique [0002] Today's circuitry places stringent demands on the processing of large amounts of data, and as a result, demands on memory performance continue to increase. However, in a radiation-resistant environment, the storage unit (bitcell) of the static random access memory (SRAM) will be flipped (upset) to cause errors in stored data. Therefore, when designing the SRAM, an error detecting and correcting (EDAC) circuit should be introduced to write back data to meet the requirements of the circuit system. [0003] Usually the EDAC circuit can correct the error in one unit, and then output the correct codeword after correction, but how many errors it can correct depends on what error correction code is used. If the wrong data stored in the...

AI Technical Summary

Problems solved by technology

The SRAM using this scheme does not need to use an error correction circuit, and can also use an error correction circuit, but the efficiency of this scheme is relatively low

If the cycle is too short, most of the data stored in the SRAM during the cycle is still correct and does not need to be written back; if the cycle is too long, most of the data in the cycle has undergone multi-bit flips, and even writing back cannot avoid data errors

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