Method for matrix operation and rigorous wave coupling analysis through parallel processing architecture

A strict wave coupling and parallel processing technology, applied in the field of matrix computing, can solve the problem of slow reading and writing of graphics card memory

Active Publication Date: 2014-03-12
RAINTREE SCI INSTR SHANGHAI
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Problems solved by technology

The stream processor reads and writes registers and shared memory quickly, but reads and writes graphics card memory slowly

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  • Method for matrix operation and rigorous wave coupling analysis through parallel processing architecture
  • Method for matrix operation and rigorous wave coupling analysis through parallel processing architecture
  • Method for matrix operation and rigorous wave coupling analysis through parallel processing architecture

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Embodiment Construction

[0090] The present invention provides a method for performing matrix operations using a parallel processing architecture, the parallel processing architecture includes a plurality of processor modules, each processor module is associated with an independent shared memory and executes an independent thread block, the method includes the following steps :

[0091] i. Each processor module executes the operation instructions in the CUDA call respectively, wherein each operation instruction corresponds to each operation part in the matrix operation one by one, and each operation part can be executed in parallel and is not related to each other;

[0092] ii. reading the data used in the operation part into the shared memory of the corresponding processor module;

[0093] iii. Each processor module reads the corresponding data in the shared memory based on the corresponding operation instruction, and executes the thread blocks in parallel to complete the operation part in the matrix...

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Abstract

The invention provides a method for matrix operation and rigorous wave coupling analysis through a parallel processing architecture, so that a matrix operation and rigorous wave coupling analysis technology which is high in speed and low in cost is provided. The parallel processing architecture comprises a plurality of processor modules which are related to independent shared storages respectively to execute independent thread blocks. The matrix operation method comprises the following steps that i, the processors modules execute operation orders called by the parallel processing architecture respectively, wherein the operation orders are in one-to-one correspondence to operation parts in matrix operation, and the operation parts can be executed in parallel and are not related to one another; ii, data used in the operation parts are read to shared storages of corresponding processor modules respectively; iii, the processor modules read corresponding data in the shared storages based on corresponding operation orders, and execute thread blocks in parallel to complete the operation parts in the matrix operation.

Description

technical field [0001] The invention relates to parallel computing, in particular to performing matrix operations based on a parallel processing architecture. Background technique [0002] With the development of high-end computer graphic display cards, multi-core graphics processing units (Graphic Processing Units, referred to as GPUs) are becoming more and more powerful. GPUs are not only optimized for displaying images, but also have inherent parallelism. Through the improvement of hardware and software, the programmability of GPU has been continuously improved, and it has surpassed the general-purpose CPU in calculation. In order to take full advantage of the powerful computing capabilities of chips, graphics card manufacturer NVIDIA has launched a new computing platform - Compute Unified Device Architecture (CUDA for short). CUDA is a general-purpose parallel processing architecture that enables GPUs to solve complex computing problems. It includes the CUDA instructio...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/16G01B11/00G01N21/88
Inventor 刘志钧徐益平施耀明
Owner RAINTREE SCI INSTR SHANGHAI
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