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Metal gate fabrication method

A technology of metal gates and manufacturing methods, which is applied in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., can solve problems affecting device performance and reliability, incomplete filling, and overhanging the top of trenches, etc., to achieve improved Functionality and reliability, and the effect of increasing the cross-sectional width

Active Publication Date: 2018-04-27
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0011] The invention provides a method for manufacturing a metal gate, which can solve the problem that when the metal gate is filled with metal, the top of the trench is likely to overhang due to the excessively large aspect ratio, resulting in too small opening, resulting in incomplete filling and affecting Device performance and reliability issues

Method used

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  • Metal gate fabrication method
  • Metal gate fabrication method
  • Metal gate fabrication method

Examples

Experimental program
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Embodiment 1

[0043] refer to Figure 3A , perform step S21, provide a semiconductor substrate 300, a dielectric layer 303 is formed on the semiconductor substrate 300, a gate dielectric layer and a dummy gate structure located on the gate dielectric layer are formed in the dielectric layer 303 305 , a spacer 304 is formed on the sidewall of the dummy gate structure 305 and the gate dielectric layer.

[0044]Wherein, the gate dielectric layer includes a tunnel oxide layer 301 and a charge storage layer 302 formed on the tunnel oxide layer 301 . The material of the dummy gate structure 305 is, for example, polysilicon, which can be formed by chemical vapor deposition or physical vapor deposition. It is used as a replacement transition for subsequent metal electrodes and will be removed in the next process. The material of the spacer 304 is, for example, silicon nitride or silicon oxide or a combination of both. The dielectric layer 303 is, for example, silicon nitride or silicon oxide or a...

Embodiment 2

[0053] refer to Figure 4A , perform step S21, provide a semiconductor substrate 400, a dielectric layer 403 is formed on the semiconductor substrate 400, a gate dielectric layer and a dummy gate located on the gate dielectric layer are formed in the dielectric layer 403 structure 405 , the dummy gate structure 405 and the sidewall of the gate dielectric layer are formed with a spacer 404 .

[0054] Wherein, the gate dielectric layer includes a tunnel oxide layer 401 and a charge storage layer 402 formed on the tunnel oxide layer 401 . The material of the dummy gate structure 405 is polysilicon, which can be formed by chemical vapor deposition or physical vapor deposition. It is used as a replacement transition for subsequent metal electrodes and will be removed in the next process. The material of the spacer 404 is, for example, silicon nitride or silicon oxide or a combination of both. The dielectric layer 403 is, for example, silicon nitride or silicon oxide or a combinat...

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PUM

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Abstract

The invention discloses a metal gate manufacturing method. The metal gate manufacturing method comprises the following steps: a semiconductor substrate with a dielectric layer formed thereon is provided, a gate dielectric layer and a virtual gate structure positioned on the gate dielectric layer are formed in the dielectric layer, and clearance walls are formed on the side walls of the virtual gate structure and the gate dielectric layer; part of the clearance walls and the virtual gate structure are removed to form grooves; metal layers are formed through a physical vapor deposition process to fill the grooves; the chemical mechanical polishing process is carried out to remove the metal layer on the dielectric layer to form a metal gate structure. The manufacturing method can form a relatively big groove opening to avoid the phenomenon that the device functions and reliability are influenced by incomplete sediment filling of the metal layer.

Description

technical field [0001] The invention relates to the field of integrated circuit manufacturing, in particular to a metal gate manufacturing method Background technique [0002] With the improvement of market requirements for semiconductor technology, the size of devices is getting smaller and smaller. The process using a silicon dioxide (SiO2) layer as a gate dielectric has reached the limit of its physical and electrical characteristics, and the silicon dioxide layer in a 65nm process transistor has shrunk to a thickness of 5 oxygen atoms. As an insulator between the gate and the underlying layer, the silicon dioxide layer cannot be shrunk any further without leakage currents that would prevent the transistor from functioning properly. In the new process, using a material with a higher dielectric constant than silicon dioxide as the new gate dielectric can solve this problem, but the new material is not compatible with the original gate polysilicon. After several tests and...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/28
CPCH01L21/28008H01L29/66545
Inventor 周鸣平延磊
Owner SEMICON MFG INT (SHANGHAI) CORP