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Array substrate, manufacturing method thereof, and display device

A technology of an array substrate and a manufacturing method, which is applied in the display field, can solve the problems of high manufacturing cost, high cost and complicated manufacturing process of a mask process, and achieve the effect of saving manufacturing process and manufacturing cost.

Inactive Publication Date: 2016-01-27
BOE TECH GRP CO LTD
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  • Abstract
  • Description
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Problems solved by technology

[0003] The manufacturing process of the TFT array substrate including this double-gate structure is more complicated than that of the array substrate of the single-gate structure TFT, and a gate layer needs to be added, so the manufacturing process needs to be increased accordingly.
make figure 1 The TFT array substrate requires 7 mask (mask) processes (7 masks from bottom to top are: bottom gate, active layer, top gate insulating layer vias, top gate and source-drain connection electrodes, insulating layer And its upper via hole, data line and source electrode, pixel electrode, figure 1 Only the top gate and the structure below it are shown in the figure), and the manufacturing cost of a mask process is high, which leads to the complicated manufacturing process and high cost of the existing array substrate including the double-gate structure TFT

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  • Array substrate, manufacturing method thereof, and display device
  • Array substrate, manufacturing method thereof, and display device
  • Array substrate, manufacturing method thereof, and display device

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Embodiment Construction

[0041] The specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. The following examples are used to illustrate the present invention, but are not intended to limit the scope of the present invention.

[0042] The method for manufacturing an array substrate according to an embodiment of the present invention includes the following steps:

[0043] Step 1: Form a pattern including the active layer, pixel electrodes and data lines on the base substrate (transparent substrate, such as a glass substrate or a quartz substrate), so that the active layer and the pixel electrodes are located on the same layer and connected to each other, and the data wires over the active layer. This step specifically includes:

[0044] like Figure 2-5 As shown, an oxide semiconductor thin film 300' and a metal thin film 200' are sequentially formed on the base substrate 100, and an oxide semi...

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Abstract

An array substrate and a manufacturing method therefor, a display device, and a thin-film transistor. The method comprises: forming on a base substrate (100) a pattern comprising an active layer (300), a pixel electrode (400), and a data line (200); forming a pattern comprising a gate insulation layer (500) and at least two gate electrode vias therein (510 and 520), where the at least two gate electrode vias (510 and 520) are located in an area in the gate insulation layer (500) corresponding to the periphery of the active layer (300) and not overlapped with areas where the pixel electrode (400) and the data line (200) are located; and, forming a pattern comprising a gate line (600) and at least two gate electrodes (610 and 620), where the at least two gate electrodes (610 and 620) are connected to the gate line (600) and are respectively located in the at least two gate electrode vias (510 and 520). The method reduces manufacturing processes and manufacturing costs.

Description

technical field [0001] The present invention relates to the field of display technology, in particular to an array substrate, a manufacturing method thereof, and a display device. Background technique [0002] For the existing oxide thin film transistor (Oxide TFT), in order to improve the stability of the thin film transistor (TFT), the TFT adopts a dual gate (Dualgate, that is, two gate) structure. like figure 1 As shown, the TFT structure includes two gates, a top gate 1 at the top and a bottom gate 2 at the bottom. Between the top gate 1 and the bottom gate 2 is an active layer formed of a gate insulating layer and an oxide. Top gate 1 and bottom gate 2 turn on the TFT at the same time. Compared with a single gate, the double gate structure has the following advantages: the channel is formed on the upper and lower sides respectively, so that the Ion current increases, and the size of the TFT can be reduced correspondingly (which can improve the transmittance); at the s...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/84H01L21/28H01L21/336H01L27/12H01L29/423H01L29/417H01L29/786
CPCH01L27/1288H01L27/1225H01L27/124H01L29/42384H01L29/78648H01L29/78696
Inventor 崔承镇金熙哲宋泳锡刘圣烈
Owner BOE TECH GRP CO LTD