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Manufacturing method for test alignment chip

A manufacturing method and a chip technology, which are applied to the photolithographic process of patterned surfaces, semiconductor/solid-state device testing/measurement, photolithographic process exposure devices, etc., can solve the problem of large number of failed chips, large influence on the actual yield of silicon wafers, The accuracy rate is not high, and the affected area is easy to control, the placement is variable, and the affected area is small.

Active Publication Date: 2014-05-21
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The number of failed chips is large, which has a great impact on the actual yield of silicon wafers, and the accuracy of judgment is not high

Method used

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  • Manufacturing method for test alignment chip
  • Manufacturing method for test alignment chip
  • Manufacturing method for test alignment chip

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Experimental program
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Embodiment Construction

[0029] In order to enable your examiner to have a further understanding and understanding of the purpose, features and effects of the present invention, the following is a detailed description of the present invention in conjunction with the accompanying drawings as follows:

[0030] The manufacturing method of the test alignment chip of the present invention includes:

[0031] Step 1. During the graphic definition at the initial stage of the process, all regions (SHOT) in the silicon wafer are exposed, such as Figure 1a As shown, where Shot is the range of one-time exposure of lithography in the chip fabrication process.

[0032] Step 2. When the chip size is too small, it is necessary to make an alignment chip. For this type of silicon chip, select a small area M at the position of the complete shot inside the silicon chip for secondary exposure, so that the area M All or part of the chips in the failure, forming a failed chip array, used as a test alignment, such as Figu...

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Abstract

The invention discloses a manufacturing method for a test alignment chip. The manufacturing method is characterized by comprising a first step of exposing all areas in a silicon wafer during graph definition at an initial stage of a process; a second step of selecting a small area M to perform secondary exposure at the complete shot position of the silicon wafer when alignment chip manufacturing is needed due to the fact that the chip size is too small, failing all the chips or some chips in the area M, and forming an invalid chip array to be used for test alignment; and a third step of judging whether test results undergo leftward, rightward, upward and downward offset relative to actual chip results on the wafer according to whether valid chips are contained in chips around the invalid chip in the area M. Compared with a conventional method for manufacturing the invalid chip in a no-exposure mode, the manufacturing method for a test alignment chip has the advantages that the influenced area is little, the judging accuracy is high, and the number change flexibility of the invalid chips is high.

Description

technical field [0001] The invention relates to a manufacturing process method of a semiconductor integrated circuit, in particular to a manufacturing method of a chip used for test alignment. Background technique [0002] In the process of electrical testing and packaging testing in the back-end of semiconductors, when the chip size is small (usually less than 2mm on a single side), the actual good / defective products will be marked on the silicon wafer due to the positional deviation of the alignment. Errors, resulting in errors in the pass / fail judgment of the final product. [0003] The usual practice is to select an incomplete exposure range at both ends of the diameter distribution of the silicon wafer in the front-end process, without exposure, and make the chips within the specified non-exposure range into invalid chips, so as to know in advance The fixed position failure chip, combined with whether the adjacent rows and columns are valid chips, is used as a determin...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/02H01L21/66G03F9/00G03F7/20
CPCG03F7/70466H01L21/027H01L22/30H01L23/544H01L2223/54426
Inventor 洪雪辉
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP