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Lateral parasitic pnp device and manufacturing method in silicon germanium hbt process

A manufacturing method and device technology, which are applied in the field of device manufacturing and lateral parasitic PNP devices, can solve problems such as device application limitations, and achieve the effects of reducing the width of the base region, increasing the DC magnification, and increasing the cut-off frequency.

Active Publication Date: 2016-08-17
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But for some applications, H FE Must be above 50, so the original design device application will be greatly limited

Method used

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  • Lateral parasitic pnp device and manufacturing method in silicon germanium hbt process
  • Lateral parasitic pnp device and manufacturing method in silicon germanium hbt process
  • Lateral parasitic pnp device and manufacturing method in silicon germanium hbt process

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Embodiment Construction

[0033] The lateral parasitic PNP device in the silicon germanium HBT process described in the present invention is described as follows in conjunction with the accompanying drawings:

[0034] like Figure 9 As shown, in the cross-sectional view, the dielectric layer 11 of the silicon germanium window is used to isolate the emitter region 9 and the collector region 6, and a shallow trench is used between the collector region 6 and the base region (ie, N-type epitaxy 3). or field oxygen isolation; where:

[0035] launch zone, yes Figure 9 The implanted region 9 shown in , is a P-type heavily doped polygonal ring in the top view of the device, wherein the active region part is the emitter region, the outside of the active region is the lead end, and in the middle of the ring-shaped emitter region is a The polygon formed by the emitter window dielectric of the silicon germanium HBT and polysilicon acts as a barrier for P-type ion implantation;

[0036] The base area is compose...

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Abstract

The invention discloses a lateral parasitic PNP device in a germanium-silicon HBT process. The lateral parasitic PNP device is provided with a barrier zone formed by an emitter zone window medium and an emitter polysilicon, so as to reduce a base zone diffusion current; an isolation zone is formed by a germanium-silicon window medium and a germanium-silicon polysilicon between the emitter zone and a collector zone; below the isolation zone, an N type epitaxy forms a base zone; and the base zone is provided with a collector sink channel. The top view of the lateral parasitic PNP device in the germanium-silicon HBT process of the invention is a polygon; the center of the emitter forms a polygon ring; the base current is reduced; the germanium-silicon medium layer is used for isolation between the emitter and the collector; the emitter area is improved and the base zone width is reduced; and the DC method multiple of the device is increased. The invention also discloses a manufacturing processing method of the germanium-silicon HBT device.

Description

technical field [0001] The invention relates to the field of semiconductor manufacturing, specifically a lateral parasitic PNP device in a germanium-silicon HBT process, and also relates to a manufacturing method of the device. Background technique [0002] The lateral parasitic PNP transistor in the conventional silicon germanium HBT process, its basic device structure is as follows figure 1 As shown, a P-type highly doped annular active region 9 is the emitter, and there is a polygonal region (the region between the emitter regions 9) in the middle, with a dielectric layer 11 and polysilicon 8 on it to block the P-type ion implantation ; The base is an N-type epitaxial region, with an N-type buried layer 2 below as a low-resistance channel, and is connected to the silicon surface by an N-type electrical sinking channel 5 on the outer ring; the collector is a P-type lightly doped Region 6; Emitter region 9 and collector region 6 are isolated by field oxygen 4 or shallow tr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/737H01L29/08H01L21/331H01L21/265
CPCH01L29/0649H01L29/0808H01L29/66242
Inventor 周正良陈曦
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP