Astronavigation FPGA universal refresh circuit based on SELECTMAP and achieving method thereof

An implementation method and circuit technology, applied in the direction of logic circuits using specific components, logic circuits using basic logic circuit components, etc., can solve problems such as internal function disorder, short-circuiting, functional failure, etc. Reliable, practical results

Active Publication Date: 2014-06-04
BEIJING MXTRONICS CORP +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This effect is the spatial single event flipping effect. The flipping of the configuration bit state may lead to serious functional failures, resulting in internal

Method used

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  • Astronavigation FPGA universal refresh circuit based on SELECTMAP and achieving method thereof
  • Astronavigation FPGA universal refresh circuit based on SELECTMAP and achieving method thereof
  • Astronavigation FPGA universal refresh circuit based on SELECTMAP and achieving method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0071] After power-on, connect the pause pin of the refresh circuit 102 to "0" level, then the refresh circuit 102 suspends work, enters and remains in the idle state 201; when the refresh circuit is in the idle state, if image 3 Shown is a schematic diagram of the internal wiring and pin levels of the refresh circuit of the present invention in an idle state. The internal wiring 301, 302, 303, and 304 are connected to connect the corresponding pins of the PROM101 and FPGA103 together, that is, the CLK tube of the PROM101 The pin is connected to the CCLK pin of FPGA103, the CE pin of PROM101 is connected to the Done pin of FPGA103, the OE pin of PROM101 is connected to the Initial pin of FPGA103, the DATA pin of PROM101 is connected to the Din pin of FPGA103; at the same time, the refresh circuit 102 D1_fpga pins, D2_fpga pins, D3_fpga pins, D4_fpga pins, D5_fpga pins, D6_fpga pins, D7_fpga pins, cs_fpga pins, write_fpga pins, and prog_fpga pins are high-impedance. At this ti...

Embodiment 2

[0073] After power-on, the pause pin of the refresh circuit 102 is connected to “1” level, the clk pin is connected to a clock signal with a fixed frequency, and the input signal of the done_fpga pin is started to be detected. If the refresh circuit 102 detects that the done_fpga level is “0”, the refresh circuit 102 will enter the configuration state 202 , otherwise it will directly jump to the readback verification state 203 . In configuration state 202, such as image 3 , the refresh circuit 102 is connected to the internal connections 301, 302, 303, 304, and the corresponding pins of the PROM101 and FPGA103 are connected together, that is, the CLK pin of the PROM101 is connected to the CCLK pin of the FPGA103, and the CE pin of the PROM101 is connected to the Done pin of the FPGA103. Pins, the OE pin of PROM101 is connected to the Initial pin of FPGA103, the DATA pin of PROM101 is connected to the Din pin of FPGA103; during the FPGA configuration process, the Done pin outp...

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Abstract

The invention relates to an astronavigation FPGA universal refresh circuit based on SELECTMAP. The refresh circuit is provided with six input pins, six output pins and eight double-direction pins, and the input pins, the output pins and the double-direction pins are connected with pins of a PROM and pins of an FPGA. The SRAM-type FPGA is subjected to backward reading operation through SELECTMAP, the type of the FPGA is determined, and backward read data are checked; if errors happen, a code stream is read from a correct data source, effective parts are intercepted from the code stream, the effective code stream is written into an inner configuration bit of the FPGA again through SELECTMAP, and accordingly refreshing of a configuration memory is completed. Through the refresh circuit, single event upset of the astronavigation FPGA can be timely detected and corrected, functional faults caused by single event upset of the astronavigation FPGA are eliminated, and astronavigation FPGA space application reliability is improved.

Description

technical field [0001] The invention relates to a SELECTMAP-based general refresh circuit for aerospace FPGAs and an implementation method thereof, in particular for detecting and recovering space single-event flipping faults that occur in SRAM-type FPGAs used in aerospace, and belongs to the technical field of integrated circuits. Background technique [0002] The basic structure of SRAM FPGA is as follows: Figure 5 , the main functional modules include: input and output modules (IOB) around the circle, two columns of block memory (Block RAM) on the edge, and internal programmable logic block array (CLB). In addition, there are connections throughout the entire circuit The interconnection resources of each module. The above logic resources and interconnect resources are all controlled by the underlying SRAM configuration bits. A large number of SRAM configuration bits all over the FPGA circuit determine the specific functions of the FPGA circuit, and the set of bit stream...

Claims

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Application Information

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IPC IPC(8): H03K19/177
Inventor 张帆陈雷赵元富文治平李学武张彦龙孙华波王硕尚祖宾冯长磊王岚施林彦君郑咸建
Owner BEIJING MXTRONICS CORP
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