Method for optimizing test wrapper scan chains of three-dimensional IP core

Abstract

The invention discloses a method for optimizing test wrapper scan chains of a three-dimensional IP core. The method is characterized by including the following steps: additionally arranging test wrapper input scan units and test wrapper output scan units, resolving a set threshold value TSV number, calculating spans of the post-bond test wrapper scan chains, merging adjacent circuit layers with the same pre-bond test wrapper scan chain numbers to form virtual layers, distributing internal scan chains, the test wrapper input scan units and the test wrapper output scan units into the test wrapper scan chains in the sequence of decreasing numbers of the virtual layers, and calculating the total time of pre-bond testing and post-bond testing of the three-dimensional IP core. By means of the method, the lengths of the pre-bond test wrapper scan chains and the lengths of the post-bond test wrapper scan chains can be balanced at the same time under constraint of the TSV number, and the aims of shortening the total time of pre-bond testing and post-bond testing of the three-dimensional IP core and reducing the hardware cost of the test wrapper scan chains are achieved.

Description

technical field [0001] The invention relates to a three-dimensional integrated circuit testing technology, in particular to an optimization method for testing a shell scanning chain in a three-dimensional IP core. Background technique [0002] With the continuous improvement of integrated circuit manufacturing technology and design technology, the feature size of transistors continues to shrink, the complexity of chips and the number of transistors gradually increase, and the interconnection lines in chips are getting longer and longer. Especially after entering the deep submicron era, the delay of interconnect lines has exceeded the delay of logic gates, becoming the main bottleneck of chip performance improvement and the main source of circuit delay and power consumption. Three-dimensional integrated circuits (Three Dimensional Integrated Circuits) vertically stack multi-layer circuits together, which can effectively reduce chip area, shorten the length of interconnection ...

AI Technical Summary

Problems solved by technology

[0009] In order to reduce the total time for pre-bond and post-bond tests of 3D IP cores, the literature D.L.Lewis, S.Panth, X.Zhao, et al, "Designing3D Test Wrappers for Pre-bond and Post-bond Test of 3D Embedded Cores", In Proceedings of IEEE International Conference on Computer Design, pp.90-95, 2011, it is proposed to use BFD (Best Fit Decreasing) and KLP (Kerninghan-Lin Partitioning) algorithms to simultaneously balance pre-binding and post-binding test shell scan chains. Length, but this method needs to increase a lot of hardware overhead to restructure the anchor chain to meet the test requirements before and after binding

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