An iterative carrier synchronization method assisted by multi-ary ldpc codes
An LDPC code and multi-ary technology, which is applied in the application of multi-bit parity error detection coding, error correction/detection using block codes, data representation error detection/correction, etc., can solve the performance and theoretical problems of LDPC codes performance gap etc.
Inactive Publication Date: 2017-03-29
SHANDONG UNIV
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Although theoretically the multi-ary LDPC code has a performance close to the Shannon limit, this is obtained under the premise of ideal coherent detection. In practical applications, unsatisfactory carrier synchronization will introduce phase deviation, and the LDPC code decoding algorithm is relatively sensitive to phase deviation. Very sensitive, which makes the performance of the LDPC code in the actual system and the theoretical performance have a big gap
The document "Code-Assisted Iterative Carrier Synchronization Algorithm Under Residual Frequency Offset Condition" discloses the use of code-assisted LDPC codes The iterative carrier synchronization method can correct the phase offset of the received information sequence without using auxiliary data, but this paper only focuses on binary LDPC code and BPSK (binary phase shift keying) modulation method
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[0069] The embodiment of the present invention is as follows, a multi-ary LDPC code-assisted iterative carrier synchronization method is applied to a multi-ary LDPC code decoder. ×n-dimensional parity check matrix H={h j,i} The determined length is a quaternary LDPC code of n, wherein the elements in the parity check matrix H and the symbol values of LDPC are taken from the Galois Field GF(4), GF(4)={0,α,α 2 ,1} where α is the multiplicative primitive element of the Galois field, and there is α in the GF(4) field 3 =1, m is the check digit length of the multi-ary LDPC code, n is the code length of the multi-ary LDPC code, h j,i It is the element of row j and column i of check matrix H, where 1≤j≤m, 1≤i≤n, M j Indicates the set of variable nodes connected to the jth check node, that is, M j ={i|h j,i ≠0}, M j \i means from M j Remove the i-th variable node set, where M represents the variable node set; N i Indicates the set of check nodes connected to the i-th variable...
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The invention discloses an iterative carrier synchronizing method based on multi-system LDPC code assistance, and belongs to the technical field of channel encoding and carrier synchronizing in digital communication. Multi-system LDPC codes have performance which is close to the ideal Shannon limit, but a decoder for the multi-system LDPC codes is quite sensitive to phase noise; the performance of the multi-system LDPC codes can extremely get worse under the condition that phase deviation occurs in the carrier. According to the method, the decoding and estimation combination is adopted, and phase deviation estimation is added to the multi-system LDPC code decoding process. Each time when decoding iteration is conducted through the decoder in the decoding process, estimation is conducted on the phase deviation; soft information produced during LDPC decoding needs to be used in estimation, then the input of the decoder is modified through estimated parameters, new soft information can be obtained after LDPC code decoding is conducted on the modified input, and the new soft information can be used for obtaining new estimation parameters; through multiple times of iteration, by means of the method, the estimation values of the parameters can be convergent into an actual value, and then the performance of the LDPC code gets close to the theoretic performance.
Description
technical field [0001] The invention relates to an iterative carrier synchronization method assisted by a multi-ary LDPC code, which belongs to the technical field of channel coding and carrier synchronization in digital communication. Background technique [0002] LDPC codes are an excellent channel codec scheme close to the Shannon limit. Multi-ary LDPC codes can be constructed when high-order Galois fields are used. Compared with binary LDPC codes, multi-ary LDPC codes have better error correction performance, can be seamlessly connected with high-order modulation methods, and have Better resistance to sudden errors. Under the condition of using Belief Propagation (BP) decoding, multi-ary LDPC codes can achieve excellent performance close to Shannon's limit. Although theoretically the multi-ary LDPC code has a performance close to the Shannon limit, this is obtained under the premise of ideal coherent detection. In practical applications, the unsatisfactory carrier sync...
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IPC IPC(8): H03M13/11
Inventor 马丕明王继来黎靖熊海良
Owner SHANDONG UNIV