Two non-overlapping clock circuits and method thereof

Abstract

Disclosed in the invention is a two-phase mutually non-overlap clock circuit comprising an input buffer unit, a first NOT gate, a first time delay unit, a second time delay unit, a first AND gate, a second AND gate, a first output buffer unit, and a second output buffer unit. The input terminal of the first NOT gate is connected with the output terminal of the input buffer unit; the input terminal of the first time delay unit is connected with the output terminal of the first NOT gate; the input terminal of the second time delay unit is connected with the output terminal of the first time delay unit; the input terminal of the first AND gate is respectively connected with the output terminal of the input buffer unit and the output terminal of the first time delay unit; the input terminal of the second AND gate is respectively connected with the output terminal of the first NOT gate and the output terminal of the second time delay unit; the input terminal of the first output buffer unit is connected with the output terminal of the first AND gate; and the input terminal of the second output buffer unit is connected with the output terminal of the second AND gate. According to the invention, the clock time delay is determined precisely by the way of capacitor introduction into the circuit; the precision and the stability are high; the non-overlap degree of the generated two-phase mutually non-overlap clock signal is good; and the integrating degree of the simulation result and the chip is high.

Description

technical field [0001] The invention relates to the technical field of circuit design, in particular to two non-overlapping clock circuits and a method thereof. Background technique [0002] The two non-overlapping clock circuits in the prior art mainly utilize the delay principle of an inverter device to generate two non-overlapping clock signals. However, under the standard CMOS process, such device delays are generally not accurate enough, and there may be a large deviation between the simulation results of the device delay and the measured values, which may lead to inconsistent non-overlapping clocks between different chips, or even It may cause a certain degree of overlap among non-overlapping clocks generated by the circuit, thereby affecting the actual performance of the switched capacitor circuit. [0003] figure 1 The two mutually non-overlapping clocks shown were published in "A Clock Generator and Output Buffer for 12bit, 75MS / s, 3.3V CMOS ADC with SFDR 85dB" by...

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Problems solved by technology

[0005] like figure 2 As shown, the clock signals generated by two non-overlapping clock circuits in the prior art will overlap to a certain extent

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