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SCR (Semiconductor Control Rectifier) _PNP (Plug N Play) structure for ESD (Electric Static Discharge) protection with strong latch resistance

An anti-latch and capability technology, applied in the electronic field, can solve the problems of difficult to meet the anti-latch design requirements, hidden danger of large latch, damage, etc., to meet the high-voltage ESD protection design requirements, strong electrostatic protection capability, and save chips area effect

Inactive Publication Date: 2014-10-29
杨变霞 +2
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  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0003] like figure 1 Shown is the traditional SCR device, which is widely used by designers because of its strongest current discharge capability and electrostatic protection capability per unit area; but it has a very low sustain voltage, and it is not easy to reach above the power supply voltage , so there is a large hidden danger of latch-up, which may easily cause the IC chip to fail to work normally or even be damaged
Traditional methods often sacrifice the electrostatic protection ability of SCR devices in exchange for their strong anti-latch-up ability, but in high-voltage circuits, it is still difficult to meet the design requirements for anti-latch-up, making it difficult for SCR devices to be used in high-voltage circuits. ESD protection design of the circuit

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  • SCR (Semiconductor Control Rectifier) _PNP (Plug N Play) structure for ESD (Electric Static Discharge) protection with strong latch resistance
  • SCR (Semiconductor Control Rectifier) _PNP (Plug N Play) structure for ESD (Electric Static Discharge) protection with strong latch resistance
  • SCR (Semiconductor Control Rectifier) _PNP (Plug N Play) structure for ESD (Electric Static Discharge) protection with strong latch resistance

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Embodiment Construction

[0019] In order to make the technical problems, technical solutions and positive effects to be solved by the present invention clearer, the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0020] A SCR_PNP structure with strong latch-up resistance for ESD protection design, such as figure 2 As shown, including: P-type substrate, insulating layer region on the substrate, N epitaxial layer region, P-type well region on the N epitaxial layer, N-type well region on the N epitaxial layer, field oxide layer region, polysilicon gate region , a thin oxide layer region, an isolation region for isolating high-voltage devices and low-voltage devices, an N-type heavily doped region, and a P-type heavily doped region. The insulating layer region is located on the top of the P-type substrate, the N-type epitaxial region is located on the top of the insulating layer region, the first P-type well region, the second P-type well regio...

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Abstract

The invention discloses an SCR (Semiconductor Control Rectifier) _PNP (Plug N Play) structure for ESD (Electric Static Discharge) protection with strong latch resistance, and belongs to the field of an electronic science and technology. When an IC (Integrated Circuit) chip is in a non-electrifying state in the process of producing, packaging, testing and the like, the SCR structure which has a very strong electric static protection capacity is started; when the chip is in an electrifying state, the PNP structure which has a very strong latch resistance is started; therefore, an electrostatic protection device has a stronger static prevention capacity and a very strong latch resistance, so as to meet the demand of high voltage ESD prevention design. According to the structure, the electrostatic protection device is stronger in static prevention capacity and stronger in latch resistance, is capable of meeting the demand of high voltage ESD prevention design, and saving the area of the chip at the same time.

Description

technical field [0001] The invention belongs to the field of electronic technology, relates to an SCR device, and in particular to an SCR_PNP structure with strong anti-latch ability for electrostatic protection (ElectroStatic Discharge, ESD for short) of IC chips. Background technique [0002] In the process of IC chip production, packaging, testing, etc., it will be exposed to a large amount of external electrostatic charges, thus forming the phenomenon of electrostatic discharge. With the shrinking of the manufacturing process and the use of various advanced processes, IC chips are more and more vulnerable to electrostatic discharge damage. In order to ensure that IC chips are not damaged during electrostatic discharge and improve the yield rate of chips, electrostatic protection design is more and more valued by IC designers. [0003] Such as figure 1 Shown is the traditional SCR device, which is widely used by designers because of its strongest current discharge capab...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/02H01L29/06H01L23/60
Inventor 杨变霞刘洋吴欣昱
Owner 杨变霞