Strong anti-latch-up controllable LIGBT (Lateral Insulated Gate Bipolar Transistor) device with ESD (Electro-Static Discharge) protective function
An ESD protection, anti-latch technology, applied in the direction of electric solid devices, semiconductor devices, electrical components, etc., can solve the problems of small maintenance voltage, power supply discharge, burning ESD protection circuit, etc., to achieve strong ESD capability, strong anti-latch The effect of lock ability
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Embodiment 1
[0022] Such as image 3 As shown, it is a structural schematic diagram of this example, including a P-type substrate 1, an insulating layer 2 located on the upper end surface of the P-type substrate 1, and an N-type epitaxial layer 3 located on the upper end surface of the insulating layer 2, and the N-type epitaxial layer 3 An isolation region 13 is arranged in the N-type epitaxial layer 3 to isolate two parts, and a first P-type well region 4 and an N-type well region 6 are arranged in the N-type epitaxial layer 3 on one side of the isolation region 13, and the The first P-type well region 4 is provided with a first N-type heavily doped region 21 and a first P-type heavily doped region 31 which are independent of each other, and the N-type well region 6 is provided with a second P-type heavily doped region. Region 32, the upper end surface of the N-type epitaxial layer 3 is provided with a field oxide layer 8 and a first thin oxide layer 10, and the first thin oxide layer 10...
Embodiment 2
[0029] Such as Image 6 As shown, in this example, on the basis of the structure of Embodiment 1, a P-sink doped region 7 is added under the first N-type heavily doped region 21 and the first P-type heavily doped region 31, and the P- The sink doped region wraps the first N-type heavily doped region 21 and the first P-type heavily doped region 31, the depth of the P-sink doped region 7 is larger than the depth of the first P-type well region 4, and the structure The doping concentration of the first P-type well region in the relative image 3 The first P-type well region of the shown structure is relatively low, which increases the withstand voltage of the LIGBT, and the doping concentration of the P-sink doped region 7 of this structure is relatively high.
[0030] The working principle of this example is the same as that of Example 1, except that the concentration of the P-sink doped region is larger than that of the P well region, so the parasitic resistance R B The volta...
Embodiment 3
[0032] Such as Figure 7 As shown, on the basis of Embodiment 1 of this example, the second P-type well region 5 is deleted, and the second N-type heavily doped region 22 and the third N-type heavily doped region 23 are changed to the third P-type heavily doped region region 33 and the fourth P-type heavily doped region 34. The polysilicon region 11 is connected to a negative low voltage source through wires.
[0033] The working principle of this example is the same as that of Example 1. The difference is that the structure of LIGBT and PMOS is used in series, and a reverse low voltage needs to be applied to the gate of PMOS to control the opening of the parasitic SCR of LIGBT.
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