A delay sampling circuit with self-calibration function

Abstract

The invention discloses a delay sampling circuit having self-calibration function. The delay sampling circuit includes a pulse generation circuit, a replication path unit, a calibration delay circuit, an edge sampling circuit, and a delay sampling control module, wherein, the replication path unit is in a variable voltage area, and other parts are in a fixed voltage area. The invention can be applied to reflect a time sequence condition of a chip and to guide voltage scaling of the chip. Two operation modes of a self-calibration mode and an adaptive voltage scaling mode are provided according to the delay sampling circuit, and cooperate with adaptive voltage scaling to operate together, which can prevent measurement deviation of the chip that results from environment change during operation, thus simultaneously giving consideration to real-time performance and reliability, and can allow the monitored circuit to operate in the required lowest voltage, thus reducing power consumption of the circuit effectively.

Description

technical field [0001] The invention relates to a delay sampling circuit with a self-calibration function, which can be used to reflect the timing deviation of a chip due to changes in technology, temperature and voltage conditions. The whole circuit is realized by pure digital logic, which belongs to the field of digital integrated circuit design. [0002] technical background [0003] With the further shrinking of the IC process size and the rapid development of handheld mobile devices, power consumption has become an important indicator in system chip design. In the traditional digital integrated circuit design process, in order to cope with the circuit changes in the worst case, the designer usually chooses the worst case as the design condition of the chip. fluctuations, process deviations (such as gate length fluctuations, doping fluctuations, etc.), coupling noise and other adverse effects of parameter fluctuations, but these adverse timing deviation factors are actua...

AI Technical Summary

Problems solved by technology

However, the stability of the oscillation ring measurement is poor, and small environmental changes can cause a large phase deviation. This overly sensitive characteristic is not conducive to the monitoring of the chip PVT; in addition, because the cycle measurement of the oscillation ring requires multiple clocks cycles to complete, the response time is relatively slow

For the monitoring unit designed by AVS, the stability and real-time performance of the oscillation ring are not competent

[0008] As a tool for monitoring unit delay, the delay sampling circuit must ensure that PVT changes will not affect the measurement results, which requires the fixed delay area to remain fixed under different PVTs, otherwise the measured replication path delay is inaccurate

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