Nanowire structure with non-discrete source and drain regions

Abstract

Nanowire structures with non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed over a substrate. Each nanowire includes a discrete channel region disposed within the nanowire. A gate electrode stack surrounds a plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of and adjacent to the discrete channel regions of the plurality of vertically stacked nanowires.

Description

technical field [0001] Embodiments of the present invention relate to the field of nanowire semiconductor devices, and more particularly to nanowire structures having non-discrete source and drain regions. Background technique [0002] The scaling of features in integrated circuits has been the driving force behind the growing semiconductor industry over the past few decades. Scaling to smaller and smaller features enables increased density of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor sizes allow an increased number of memory devices to be combined on a chip, resulting in the manufacture of products with increased capacity. However, the incentive for greater capacity is not without its problems. The need to optimize the performance of each device becomes increasingly important. [0003] Sustaining increased mobility and short channel control as microelectronic device dimensions scale beyond the 15 nanometer (nm) ...

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Problems solved by technology

[0003] Sustaining increased mobility and short channel control as microelectronic device dimensions scale beyond the 15 nanometer (nm) node presents challenges in device fabrication

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