FPGA dynamic power consumption estimation method based on BP neural network

A BP neural network and dynamic power consumption technology, applied in energy-saving computing, software testing/debugging, climate sustainability, etc., can solve problems such as learning rate improvement and long learning time

Active Publication Date: 2014-12-10
XIAN INSTITUE OF SPACE RADIO TECH
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Problems solved by technology

The learning speed adaptive adjustment method ensures that the BP neural network can choose the maximum value within the allowable range of the learning rate for learning, but the learning time is still long
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  • FPGA dynamic power consumption estimation method based on BP neural network
  • FPGA dynamic power consumption estimation method based on BP neural network
  • FPGA dynamic power consumption estimation method based on BP neural network

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Embodiment Construction

[0049] Specific embodiments of the present invention will be further described in detail below in conjunction with the accompanying drawings.

[0050] Such as figure 1 As shown, a method for estimating dynamic power consumption of FPGA based on BP neural network. The dynamic power consumption of FPGA mainly comes from four modules, which are clock tree, programmable resource, I / O (input and output port), and block memory. Including the following steps:

[0051] (1) According to XPE (XPower Estimator), the sample data of four modules are respectively obtained, that is, the input and output volume of each module; FPGA has many modules, but all of them include these four modules, and the dynamic power consumption of these four modules is The ratio is relatively large, so the present invention only considers these four modules. The sample data refers to the input and output quantities considered when estimating the power consumption of each module.

[0052] The specific steps t...

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Abstract

The invention discloses an FPGA dynamic power consumption estimation method based on a BP neural network. The FPGA dynamic power consumption estimation method comprises the following steps that (1) the input and output quantities of four modules are obtained as sample data; (2) data screening and data preprocessing are carried out on the sample data; (3) BP neural network models of the four modules are respectively constructed according to the processed sample data; (4) part of the sample data are adopted as the training data of the BP neural network, the trained neural network is obtained after BP neural network training is carried out, and then power consumption of neural network output is obtained; (5) the sample data with the training data removed are adopted as the testing data of the BP neural network, and the obtained power consumption is compared with the testing data; (6) the power consumption output by the neural network is restored to be actual power consumption values; (7) the obtained power consumption estimation values of the four modules are summated to obtain a total power consumption value. The power consumption values can be accurately predicted through automatic study of the BP neural network.

Description

technical field [0001] The invention relates to an FPGA dynamic power consumption estimation method based on a BP neural network, and belongs to the technical field of FPGA dynamic power consumption estimation. Background technique [0002] FPGA power consumption generally consists of static power consumption and dynamic power consumption. The static power consumption is mainly caused by the leakage current of the transistor, which is related to the process; the dynamic power consumption is mainly caused by the charging and discharging of the capacitor, which is mainly reflected in the power consumed by the clock, programmable resources, I / O, and BRAM. In general, dynamic power consumption accounts for a large proportion of total power consumption, so generally speaking, only dynamic power consumption is considered in FPGA power consumption. [0003] At present, mainstream FPGA suppliers provide related software to calculate power consumption, such as Xilinx’s Xpower power ...

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Application Information

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IPC IPC(8): G06F1/32G06F11/36G06F11/34
CPCY02D10/00
Inventor 袁雅婧巨艇贾亮郭宝龙徐芳
Owner XIAN INSTITUE OF SPACE RADIO TECH
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