SRAM unit

Abstract

The invention relates to an SRAM (static random access memory) unit, which includes a first inverter and a second inverter that are cross coupled to form a first storage node and a second storage node. The grids of a first transmission transistor and a second transmission transistor are electrically connected to a first word line, the grids of a third transmission transistor and a fourth transmission transistor are electrically connected to a second word line, and the grids of a fifth transmission transistor and a sixth transmission transistor are electrically connected to a third word line. The sources of the first transmission transistor and the second transmission transistor are electrically connected to a first bit line and a second bit line respectively, the sources of the third transmission transistor and the fourth transmission transistor are electrically connected to a third bit line and a fourth bit line respectively, and the sources of the fifth transmission transistor and the sixth transmission transistor are electrically connected to a fifth bit line and a sixth bit line respectively. The drain electrodes of the first transmission transistor, the third transmission transistor and the fifth transmission transistor are in electric connection with the first storage node, and the drain electrodes of the second transmission transistor, the fourth transmission transistor and the sixth transmission transistor are in electric connection with the second storage node. Thus, the read-write speed of SRAM can be greatly improved.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an SRAM unit. Background technique [0002] Static Random Access Memory (SRAM), as a member of memory, has the advantages of high speed, low power consumption and compatibility with standard processes, and is widely used in PCs, personal communications, consumer electronics (smart cards, digital cameras, Multimedia player) and other fields. [0003] refer to figure 1 , figure 1 It is a circuit structure diagram of an SRAM unit containing six transistors (6-T) in the prior art, and the SRAM unit of the 6T structure includes: a first PMOS transistor PU1, a second PMOS transistor PU2, a first NMOS transistor PD1, and a first NMOS transistor PD1. The second NMOS transistor PD2, the third NMOS transistor PG1, and the fourth NMOS transistor PG2. The first PMOS transistor PU1 and the first NMOS transistor PD1 form a first inverter, the second PMOS transistor PU2 and the secon...

AI Technical Summary

Problems solved by technology

[0008] The problem solved by the present invention is that, with the continuous increase of the amount of data information in modern society, the existing 6TSRAM unit can no longer meet the requirements for higher read and write frequency of SRAM

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