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Method and apparatus for wafer testing

A technology of test mode and test sequence, which can be used in measuring devices, electronic circuit testing, components of electrical measuring instruments, etc., and can solve the problems of increasing test time and test cost.

Active Publication Date: 2018-03-23
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Test time and cost of test increase dramatically due to increased requirements for more test patterns on a single die

Method used

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  • Method and apparatus for wafer testing
  • Method and apparatus for wafer testing
  • Method and apparatus for wafer testing

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Embodiment Construction

[0031] The making and using of various embodiments of the invention are discussed in detail below. It should be appreciated, however, that the various embodiments provide many applicable inventive innovations that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are illustrative only, and do not limit the scope of the invention.

[0032] The description of the exemplary embodiments is intended to be read in conjunction with the accompanying drawings, which are considered a part of the entire written description. In this description, relative terms such as "below", "upper", "horizontal", "vertical", "above", "below", "upward", "downward", "top" and "bottom" and their Derivatives (eg, "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to orientations as subsequently described or as shown in the figures in question. These relative terms are for convenience of description, but do not require that the device be c...

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Abstract

The invention provides a system for testing a wafer, including a probe card and a wafer. The probe card includes at least one first probe site and at least one second probe site. A wafer includes a plurality of dies. At least one first probe site is configured for a first test, and at least one second probe site is configured for a second test. Each of the plurality of dies corresponds to a first probe pad and a second probe pad. Each of the at least one first probe site is configured to contact a first probe pad of each of the plurality of dies. Each of the at least one second probe site is configured to contact a second probe pad of each of the plurality of dies. The invention also discloses a wafer testing method and device.

Description

technical field [0001] The present invention relates to integrated circuits (ICs), and more particularly to integrated circuit wafer testing. Background technique [0002] In the manufacture of semiconductor integrated circuits (ICs), wafers are tested to ensure proper functioning during fabrication and prior to shipment. Wafer testing is a testing technique in which temporary electrical connections are made between automatic test equipment (ATE) and dies formed on a wafer to verify proper performance of ICs. [0003] With increasing complexity of circuit design, rapid development of semiconductor manufacturing processes, and demands on circuit performance, ICs with three-dimensional (3D) structures have been developed to improve circuit performance. There are many different processes required to fabricate 3DICs including grinding, etching, milling, various deposition techniques, etc. These processes generate electrical charges on the fabricated devices. As the requiremen...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R1/073G01R31/28H01L21/66
CPCG01R31/318511G01R31/2889G01R31/318513
Inventor 王敏哲彭经能林鸿志陈颢李尚儒
Owner TAIWAN SEMICON MFG CO LTD