Multiplying unit

Abstract

The invention is suitable for the field of digital encoding, and provides a digital parallel multiplying unit. The multiplying unit comprises an input end A, an input end B0...BP-2BP-1, an output end C and a calculating unit, wherein the input end A and the input end B0...BP-2BP-1 input into the calculating unit respectively, and output from the output end C of the calculating unit after calculation and processing; an output calculating formula of the calculating unit is shown as C=R(AB0+AB1*<d>+...+ABp-1*<d(p-1)>)modF(x); in the formula, R is a non-zero polynomial, x is a radical of an irreducible polynomial F(x), d is a segmentation length, p is a segment number, and mod F(x) refers to reduction, namely, modulus operation of an obtained result. The multiplying unit mentioned in the application has the advantages of low space complexity, small area, low power consumption, increase of the calculating efficiency and expansibility.

Description

technical field

[0001] The invention belongs to the field of digital coding, and in particular relates to a low-complexity digital serial multiplier which can be expanded into a polynomial base multiplier. Background technique

[0002] Applications such as Diffie-Hel Iman key exchange, digital signatures, elliptic curve ciphers, and pairing ciphers all involve finite-field multiplier computations. For pairing ciphers, the pairing of Weil and Tate based on elliptic curve operations requires a lot of calculations, and its operating parameters belong to super-large finite fields. For example, for a 128-bit heap cipher to be secure, Tate pairings based on supersingular elliptic curves need to be in the composite field GF(2 4×1223 ) to perform operations. Therefore, how to efficiently design multiplication operations over very large finite fields on hardware is a great challenge, especially on hardware with limited resources.

[0003] For GF(2 m ) hardware implementation of f...

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