B4-Flash with convexity grid electrode structure

Abstract

The invention relates to a non-volatile memory, in particular to a B4-Flash with a convexity grid electrode structure. The convexity grid electrode structure successively comprises a tunnel oxide layer, an electric charge storage layer, a dielectric barrier layer and a conducting layer from bottom to top, wherein the tunnel oxide layer is of a convexity type structure of which two sides of the top surface bulge to the middle; meanwhile, the electric charge storage layer is of an arch bridge shaped structure, wherein two sides of the top surface edge of the arch bridge shaped structure bulge to the middle, and the bottom surface of the arch bridge shaped structure sink to the middle from two sides; the electric charge storage layer is integrally covered on the upper surface of the tunnel oxide layer. According to the B4-Flash with the convexity grid electrode structure, the convexity grid electrode structure is adopted in the B4-Flash, so that tunneling from the electric charge storage layer to a substrate is greater than the tunneling injected into the electric charge storage layer from a gate pole so as to inhibit even eliminate and erase saturation and improve erasing speed.

Description

technical field [0001] The invention relates to a nonvolatile memory, in particular to a B4-Flash with a convex gate structure. Background technique [0002] Flash memory is a type of non-volatile memory device. Traditional flash memory uses a floating gate to store data, and the floating gate is generally made of polysilicon (poly) material. [0003] For NOR flash memory cells, the most important limit to the continued reduction in size is the shortening of the gate length. This is mainly because the channel hot electrons (CHE) injection compilation method requires a certain voltage at the drain terminal, and this voltage has a great influence on the penetration of the source and drain terminals. For short-channel devices, the channel heat Electronic means are not applicable. Another problem is that this limits the programming rate of NOR flash compared to NAND and AND data storage devices. According to the prediction of the document "G. Servalli, et al., IEDM Tech. Dig....

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Problems solved by technology

[0007] Existing problems in the existing technology: Because the existing floating gate B4-Flash technology still adopts a planar gate structure, there is a problem of erase saturation

However, since this structure is the same as the traditional Flash structure, the floating gate dielectric material and the upper and lower surfaces of the floating gate are all on the same level, so in the programming process, the distribution of its electric force lines is the same as that of the floating gate. figure 1 Shown is exactly the same, so there is still the problem of wipe saturation

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