A b4‑flash with a convex gate structure

Abstract

The present invention relates to a non-volatile memory, in particular to a B4-Flash with a convex gate structure. The gate structure is sequentially composed of a tunnel oxide layer, a charge storage layer, a blocking dielectric layer and a conductive layer from bottom to top; wherein, The tunnel oxide layer is a convex structure with the top surface raised from both sides to the middle; at the same time, the charge storage layer is an arch bridge structure with the top surface raised from both sides to the middle and the bottom surface is concave from both sides to the middle, and completely covers the The upper surface of the tunnel oxide layer; the charge storage layer is a silicon nitride layer, the amount of nitrogen at the upper and lower positions of the silicon nitride layer is equal, and the silicon content at the upper and lower positions is also equal. The present invention can make the tunneling from the charge storage layer to the substrate larger than the tunneling injected into the charge storage layer from the gate, thereby suppressing or even eliminating erasing saturation and increasing the erasing speed.

Description

technical field [0001] The invention relates to a nonvolatile memory, in particular to a B4-Flash with a convex gate structure. Background technique [0002] Flash memory is a kind of non-volatile memory device. Traditional flash memory uses floating gate to store data, because the floating gate is made of polysilicon. [0003] For NOR flash memory cells, the most important limit to the continued reduction in size is the shortening of the gate length. This is mainly because the channel hot electrons (CHE) injection compilation method requires a certain voltage at the drain terminal, and this voltage has a great influence on the penetration of the source and drain terminals. For short-channel devices, the channel heat Electronic means are not applicable. Another problem is that this limits the programming rate of NOR flash compared to NAND and AND data storage devices. According to the prediction of the document "G. Servalli, et al., IEDM Tech. Dig., 35_1, 2005", the physi...

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Problems solved by technology

When the two tunneling speeds are equal, the loss and injection of electrons in the charge storage polysilicon layer reach a dynamic balance, and enter the state of erasing saturation, so that the erasing cannot continue, and the erasing speed decreases

[0007] Existing problems in the existing technology: Because the existing floating gate B4-Flash technology still adopts a planar gate structure, there is a problem of erase saturation

However, since this structure is the same as the traditional Flash structure, the floating gate dielectric material and the upper and lower surfaces of the floating gate are all on the same level, so in the programming process, the distribution of its electric force lines is the same as that of the floating gate. figure 1 Shown is exactly the same, so there is still the problem of wipe saturation

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