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Multilayer Substrates for Semiconductor Packaging

A semiconductor and substrate technology, applied in the direction of semiconductor devices, semiconductor/solid-state device manufacturing, semiconductor/solid-state device components, etc., can solve problems such as the reliability of thin conductive traces

Active Publication Date: 2019-04-09
ADVANPAK SOLUTIONS PTE
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, such etched patterned leadframes are not suitable for use with chips that require thinner and tighter conductive traces than conventional leadframes
The etch process inherently causes undercuts, and the resulting thin conductive traces can have reliability issues for high-volume manufacturing

Method used

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  • Multilayer Substrates for Semiconductor Packaging
  • Multilayer Substrates for Semiconductor Packaging
  • Multilayer Substrates for Semiconductor Packaging

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Embodiment Construction

[0018] One or more specific and alternative embodiments of the invention will now be described with reference to the accompanying drawings. It will be apparent, however, to one skilled in the art that the present invention may be practiced without such specific details. Certain details may not be described in detail so as not to obscure the invention. For ease of reference, when referring to the same or similar features common to the drawings, a common reference number or series of numbers will be used throughout the drawings.

[0019] Figures 1A-1J A stepwise formation process of a multilayer substrate 105 comprising two layers of conductor traces is shown in accordance with an embodiment of the present invention. Such as Figure 1A As shown, the first step in process 100 is to provide a carrier 110 having a first surface and an oppositely facing second surface. Preferably, the carrier 110 is made of a material with a relatively high Young's modulus of elasticity, the ca...

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Abstract

The invention provides a semiconductor substrate (105, 105a) comprising two or more stacked structural layers (120, 220) formed on a sacrificial carrier (110). Each built-up structural layer includes a conductor trace layer (114a) and an interconnection layer (118a, 218a), the structural layers being molded in a resin molding compound. The top surface of the molding compound is ground and then deposited from an adhesive layer (123, 124, 224). The multilayer substrate (105, 105a) may then be obtained after the outermost conductor trace layer (128a, 228a) is formed on the adhesive layer and the carrier (110) or stiffener ring (110b) is removed.

Description

technical field [0001] The present invention relates to multilayer substrates for semiconductor packaging and methods of making such substrates. Background technique [0002] Conventional semiconductor chips are mounted on lead frames. These lead frames are typically formed by coating the copper substrate with a layer of photoresist, exposing the pattern on the photoresist layer using a mask, removing the photoresist layer positively or negatively, and then etching away the copper to give the patterned lead frame. However, such patterned leadframes formed by etching are not suitable for use with chips that require thinner and tighter conductive traces than conventional leadframes. The etch process inherently causes undercuts, and the resulting thin conductive traces can have reliability issues for high-volume manufacturing. [0003] US Patent No. 7,795,071 issued to Singapore's Advanced Packaging Solutions Pte Ltd (Advanpack Solutions) describes a method of forming a sing...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/498H01L21/48
CPCH01L23/13H01L23/49822H01L21/4857H01L24/97H01L2224/16225H01L2224/32225H01L2224/48091H01L2224/48227H01L2224/73204H01L2224/73265H01L2924/15311H01L2224/97H01L2924/15747H01L2924/181H01L2924/12042Y10T29/49121H01L2924/00014H01L2924/00H01L2924/00012H01L21/4842H01L21/56H01L23/12H01L23/295H01L23/49838
Inventor 林少雄周辉星
Owner ADVANPAK SOLUTIONS PTE