An Optimized Flash Memory Address Mapping Method

A technology of address mapping and flash memory, which is applied in the field of optimized flash memory address mapping to simplify the access process, save cache access time, and improve utilization

Active Publication Date: 2017-05-03
LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

It is worth noting that there are only 4 items of address mapping information actually updated, but it causes update operations corresponding to 4 conversion pages
Therefore, when there are many valid data pages in the collection block, garbage collection will incur a large amount of translation page update overhead

Method used

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  • An Optimized Flash Memory Address Mapping Method
  • An Optimized Flash Memory Address Mapping Method
  • An Optimized Flash Memory Address Mapping Method

Examples

Experimental program
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Embodiment Construction

[0036] Below according to accompanying drawing of description, in conjunction with specific embodiment, the present invention is further described:

[0037] An optimized flash memory address mapping method, in the demand-based page-level address mapping (DFTL) method, a global translation page mapping table GTD is maintained in the memory, and at the same time, the address mapping cache CMT is used in the memory to cache the conversion For frequently accessed address mapping items in a page, the data unit of the cache is the entire address translation page, which unifies the granularity of the address mapping information in the flash memory and the cache, and each address translation page contains the mapping information of the 1MB address space. For frequent access to local data, you only need to access the page-level address mapping cache without accessing the flash memory; at the same time, when a translation page needs to be replaced out of the cache, all the updated addres...

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PUM

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Abstract

The invention discloses an optimized flash memory address mapping method. In the demand-based page-level address mapping DFTL method, a global conversion page mapping table GTD is maintained in the memory, and at the same time, the address mapping cache CMT is used in the memory to cache Address mapping items that are frequently accessed in the translation page, wherein the cached data unit is the entire address translation page. The present invention unifies the granularity of the address mapping information in the flash memory and the cache, fully utilizes the temporal locality and spatial locality of the data, such as frequent access to local data in a short period of time, only needs to access the page-level address mapping cache without accessing the flash memory, At the same time, when a conversion page needs to be replaced out of the cache, all updated address mapping information can be updated to the flash memory at the same time, which improves the utilization rate of the mapping information.

Description

technical field [0001] The invention relates to the technical field of flash memory, in particular to an optimized flash memory address mapping method. Background technique [0002] With the development and maturity of flash memory technology, flash memory has been widely used in various storage systems, such as U disk, smart phone, tablet computer, digital memory card, solid state drive, etc. Compared with traditional disk storage, flash memory has the advantages of high read and write performance, non-volatility, low power consumption, high density and good shock resistance. Therefore, flash memory has become a storage medium for mobile embedded devices. However, flash memory also has some limitations, such as "off-site update" and limited block erase times. In order to solve these deficiencies and make flash memory work like a traditional block device, an embedded software called flash translation layer (FTL) appears in the flash memory storage system, which is used to ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/02G06F12/0866G06F12/1009
CPCG06F12/0246G06F2212/7201
Inventor 杨晋博尹艳艳张新玲
Owner LANGCHAO ELECTRONIC INFORMATION IND CO LTD
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