Instruction set architecture with extensible register addressing

Abstract

A method and circuit arrangement selectively source and / or write data from / to extended registers of an extended register file based in part on whether an operand address of an instruction references a primary register of primary register file configured to store a pointer to the extended register. Control logic connected to the primary register file and the extended register file determines whether the operand address references a primary register configured to store a pointer, and responsive to the determination, the control logic causes execution logic to selectively source and / or write data from / to the extended register pointed to by the pointer stored in the referenced primary register.

Description

technical field [0001] The present invention relates generally to data processing and in particular to instruction set architectures for processors and computers incorporating these instruction set architectures. Background technique [0002] The basic task of every computer processor is to execute computer programs. How a processor handles this task and how computer programs must present themselves to the processor for execution is governed by both the processor's microarchitecture and instruction set architecture (ISA). An ISA is similar to a programming model and primarily concerns how instructions in a computer program should be formatted to be properly decoded and executed by a processor, but an ISA can also specify other aspects of a processor such as native data types, registers, addressing modes , memory architecture, interrupt and exception handling, and external I / O. The microarchitecture primarily governs the lower-level details of how instructions are decoded a...

AI Technical Summary

Problems solved by technology

However, destructive operations often inconvenience compilers and software engineers because it is often necessary to keep additional copies of the source data to be overwritten by destructive operations separately in scratch registers, which in addition to using valuable scratch register space May have potential performance issues

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