The method of mipi module dsi clock reconfiguration based on fpga

Abstract

The invention discloses an FPGA (field programmable gate array)-based MIPI (mobile industry processor interface) module DSI clock reconfiguration realizing method. The method includes the steps of 1) determining a value of a multiplier N between an input clock and an output clock of an FPGA, wherein the output clock and the input clock of the FPGA satisfy the equation FCLKOUT=FCLKIN X N; 2) setting a value of DSI clock frequency FDSI needing to be configured into a DSI clock frequency configuration parameter; 3) invoking the DSI clock frequency configuration parameter and calculating a multiplier parameter m of the DSI clock frequency FDSI needing to be configured and an input clock fin of a clock management chip, wherein the m satisfies the equation that m=FDSI / (finXN); 4) converting the adjusting multiplier parameter m of the clock management chip into a clock management chip register configuration data format, wherein the relation between an output clock and the input clock fin of the clock management chip satisfies the equation that fout=finXm; 5) enabling the FPGA to receive the output clock fout of the clock management chip, namely, enabling the input clock FCLKIN of the FPGA to satisfy the equation that FCLKIN=fout=finXm and enabling the output clock FCLKOUT of the FPGA to satisfy the equation that FCLKOUT=FCLKIN X N=finXmXN=FDSI, so that the condition that the output clock FCLKOUT of the FPGA is equal to the DSI clock frequency FDSI needing to be configured is realized.

Description

technical field [0001] The invention relates to the technical field of MIPI module DSI clock frequency, in particular to a method for realizing MIPI module DSI clock reconfiguration based on FPGA. Background technique [0002] The MIPI test module needs to adjust the DSI clock frequency when testing MIPI modules with different sizes or resolutions. Since the clock frequency of DSI is very wide, ranging from 62.5MHz to 1.1GHz, the same test equipment needs to be able to adjust the DSI clock in real time when testing different MIPI modules. The signal source of MIPI module test equipment is generated by FPGA, and the DSI clock is provided by FPGA. [0003] At present, there are usually two methods for FPGA to obtain the desired output clock: [0004] 1) The first method is to use an oscillator or a clock buffer (buffer) to provide a fixed differential or single-ended clock to the FPGA, and then use the internal PLL (phase-locked loop) of the FPGA to generate the required clo...

AI Technical Summary

Problems solved by technology

[0013] Therefore, it is necessary to know f out value, the clock management chip can correctly configure the output clock, and an additional control interface is required. It can be seen that the steps of this method to obtain the correct DSI clock are cumbersome and not real-time

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