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Multichannel synchronization and offset controllable circuit in single logic chip

A logic chip and multi-channel technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of no synchronization relationship, difficulty in meeting comprehensive performance requirements, multi-channel determinism and real-time performance cannot be guaranteed, and achieve real-time improvement Effect

Inactive Publication Date: 2015-03-25
AVIC NO 631 RES INST
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  • Abstract
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Problems solved by technology

[0003] Most of the circuits currently used contain only one 1394 node in one chip, and there is no synchronization relationship between multiple channels. Since there is no synchronization relationship between multiple channels, the determinism and real-time performance of multi-channel joint work cannot be guaranteed, and it is difficult to meet the increasing comprehensive requirements. Therefore, it is urgent to provide a circuit with multi-channel synchronization and channel skew controllable in a chip

Method used

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  • Multichannel synchronization and offset controllable circuit in single logic chip
  • Multichannel synchronization and offset controllable circuit in single logic chip

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Embodiment Construction

[0013] The technical solutions of the present invention are clearly and completely described below in conjunction with the accompanying drawings and specific embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without making creative work are all Belong to the protection scope of the present invention.

[0014] like figure 1 As shown, this embodiment provides a multi-channel synchronization and channel offset controllable circuit, which mainly includes the following modules:

[0015] Host interface: The host interface adopts the standard PCI bus interface, which complies with the PCIv2.2 electrical specification and does not support hot swapping. The PCI slave interface module works as a slave device of the bus. The PCI host interface is mainly responsible for filling in the configuration tab...

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Abstract

The invention provides a multichannel synchronization and offset controllable circuit in a single logic chip. The multichannel synchronization and offset controllable circuit comprises a main unit interface module, a DMA (direct memory access) module, a configuration table transmitting and receiving list DPRAM (dual port random access memory) module, a data DPRAM module, an AS5643 protocol processing module and a global control module. The configuration table transmitting and receiving list DPRAM module, the data DPRAM module, the AS5643 protocol processing module can realize three AS5643 node functions, a global register can dispatch uniformly and start transmission, synchronous control of the three nodes is realized, and the multichannel synchronization and offset controllable circuit can be realized and used for AS5643 protocol node communication.

Description

technical field [0001] The invention belongs to the field of computer application technology, and in particular relates to AS5643 protocol node machine communication. Background technique [0002] The AS5643 protocol is the core and foundation of the 1394 bus network, so the communication between AS5643 protocol nodes is very important. With the continuous development of avionics equipment, there are more and more external devices on the 1394 bus network, and the functions are becoming more and more complex. The performance requirements for data transmission bandwidth, determinism, and real-time performance are also getting higher and higher. [0003] Most of the circuits currently used contain only one 1394 node in one chip, and there is no synchronization relationship between multiple channels. Since there is no synchronization relationship between multiple channels, the determinism and real-time performance of multi-channel joint work cannot be guaranteed, and it is diffi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/28
CPCG06F13/4072G06F13/4295G06F2213/0012
Inventor 田泽牛少平韩一鹏郑斐夏大鹏
Owner AVIC NO 631 RES INST
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