A stacked cache system, control method and cache device based on sedram

A stacking and controller technology, applied in the field of Cache devices and stacked Cache systems, can solve the problems of low SRAM integration, large SRAM volume, and large cache capacity, and achieves increased data transmission bandwidth, strong computing power, and accelerated The effect of read speed

Active Publication Date: 2021-05-28
BEIJING VCORE TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The integration of SRAM is low, and the same capacity of DRAM (Dynamic Random Access Memory, dynamic random access memory) memory can be designed to be smaller, but SRAM requires a large volume, and the price is relatively high. An important reason for increasing the cache capacity. The increase in capacity will inevitably lead to an increase in the number of transistors inside the CPU. To integrate a larger cache on a limited CPU area, the manufacturing process is more demanding.

Method used

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  • A stacked cache system, control method and cache device based on sedram
  • A stacked cache system, control method and cache device based on sedram
  • A stacked cache system, control method and cache device based on sedram

Examples

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Embodiment 1

[0075] refer to figure 1 , image 3 , this embodiment provides a stacked Cache system based on SEDRAM, the stacked Cache system is integrated in a multi-layer bonded wafer, and includes a cache memory (Cache), a Cache controller, and a SEDRAM controller; the SEDRAM controller can It can be single-channel or multi-channel parallel access; according to the number of SEDRAM banks, there can be one or more SEDRAM controllers;

[0076] The multilayer bonded wafer includes a storage wafer structure and a processor wafer structure, the storage wafer structure includes at least one layer of storage wafer, and the processor wafer structure includes at least one layer of processor wafer; that is: multilayer bonding A wafer can include a processor wafer and a storage wafer, a multi-layer bonded wafer can also include a processor wafer and two storage wafers, and a multi-layer bonded wafer can also include two layers The processor wafer and one layer of storage wafer, the specific numbe...

Embodiment 2

[0083] refer to figure 2 , Figure 4 , this embodiment provides a stacked Cache system based on SEDRAM, the stacked Cache system is integrated in a multi-layer bonded wafer, and includes a cache memory (Cache), a Cache controller, and a SEDRAM controller; the SEDRAM controller can It can be single-channel or multi-channel parallel access; according to the number of SEDRAM banks, there can be one or more SEDRAM controllers;

[0084] The multilayer bonded wafer includes a storage wafer structure and a processor wafer structure, the storage wafer structure includes at least one layer of storage wafer, and the processor wafer structure includes at least one layer of processor wafer; that is: multilayer bonding A wafer can include a processor wafer and a storage wafer, a multi-layer bonded wafer can also include a processor wafer and two storage wafers, and a multi-layer bonded wafer can also include two layers The processor wafer and one layer of storage wafer, the specific num...

Embodiment 3

[0093] refer to Figure 5 , this embodiment provides a Cache control method for any stacked Cache system in the above embodiments, using the SEDRAM unit integrated in each layer of the storage wafer in the storage wafer structure as the Cache system The overall storage space of the Cache is controlled, and both the control domain and the Cache data domain are stored in the SEDRAM unit;

[0094] The concrete steps of this Cache control method are as follows:

[0095] First step S10: the CPU integrated in the processor wafer structure outputs a memory access address;

[0096] Second step S11: According to the memory access address, the Cache controller sends a read request to the SEDRAM controller integrated in the processor wafer structure, and the SEDRAM controller reads the required Cache Line from the SEDRAM unit. The Cache Line includes the control domain and Cache data domain (Cache Data), control domain includes Cache state domain (Cache State) and Cache tag domain (Cac...

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Abstract

The present invention involves a stacking Cache system, control method, and Cache device based on SEDRAM. The stack Cache system is integrated in multi -layer keyheets, including high -speed buffer storage, Cache controller and SEDRAM controller; multi -layer keysHead wafer includes the wafer structure and processor wafer structure; the SEDRAM unit is integrated in each layer of memory wafers in the memory wafer structure, and is used as a storage space for high -speed buffer storage storage;, Cache controller, SEDRAM controller and memory controller.The above CACHE system uses the SEDRAM unit integrated on each layer of the storage wafer structure as a storage space for high -speed buffer storage storage, which can greatly increase the capacity and bandwidth of the high -speed buffer storage memory, increase the hit rate of high -speed buffer storage, speed up hot data dataReading speed, increase the hit rate of data reading data inside the CPU, and can also save the storage resources of the processor chip.

Description

technical field [0001] The invention relates to the technical field of computer memory, in particular to a stacked Cache system based on SEDRAM, a control method and a Cache device. Background technique [0002] In the prior art, cache memory (Cache) is a small-capacity high-speed memory composed of fast SRAM (Static Random-Access Memory) storage elements, which can be directly integrated in a CPU (Central Processing Unit, central processing unit) chip. A high-speed cache is set between the CPU and the memory, and the frequently accessed active program blocks and data blocks in the memory are copied to the cache to improve the speed of CPU read and write instructions and data. Due to the locality of program access, in most cases, the CPU can directly obtain instructions and data from the Cache without accessing the memory. [0003] The integration of SRAM is low, and the same capacity of DRAM (Dynamic Random Access Memory, dynamic random access memory) memory can be designe...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F3/06G06F9/50
CPCG06F3/0604G06F3/0614G06F3/0622G06F3/0656G06F9/5027Y02D10/00
Inventor 赵继业郇丹丹
Owner BEIJING VCORE TECH CO LTD
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