A stacked cache system, control method and cache device based on sedram

Abstract

The present invention involves a stacking Cache system, control method, and Cache device based on SEDRAM. The stack Cache system is integrated in multi -layer keyheets, including high -speed buffer storage, Cache controller and SEDRAM controller; multi -layer keysHead wafer includes the wafer structure and processor wafer structure; the SEDRAM unit is integrated in each layer of memory wafers in the memory wafer structure, and is used as a storage space for high -speed buffer storage storage;, Cache controller, SEDRAM controller and memory controller.The above CACHE system uses the SEDRAM unit integrated on each layer of the storage wafer structure as a storage space for high -speed buffer storage storage, which can greatly increase the capacity and bandwidth of the high -speed buffer storage memory, increase the hit rate of high -speed buffer storage, speed up hot data dataReading speed, increase the hit rate of data reading data inside the CPU, and can also save the storage resources of the processor chip.

Description

technical field [0001] The invention relates to the technical field of computer memory, in particular to a stacked Cache system based on SEDRAM, a control method and a Cache device. Background technique [0002] In the prior art, cache memory (Cache) is a small-capacity high-speed memory composed of fast SRAM (Static Random-Access Memory) storage elements, which can be directly integrated in a CPU (Central Processing Unit, central processing unit) chip. A high-speed cache is set between the CPU and the memory, and the frequently accessed active program blocks and data blocks in the memory are copied to the cache to improve the speed of CPU read and write instructions and data. Due to the locality of program access, in most cases, the CPU can directly obtain instructions and data from the Cache without accessing the memory. [0003] The integration of SRAM is low, and the same capacity of DRAM (Dynamic Random Access Memory, dynamic random access memory) memory can be designe...

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Problems solved by technology

[0003] The integration of SRAM is low, and the same capacity of DRAM (Dynamic Random Access Memory, dynamic random access memory) memory can be designed to be smaller, but SRAM requires a large volume, and the price is relatively high. An important reason for increasing the cache capacity. The increase in capacity will inevitably lead to an increase in the number of transistors inside the CPU. To integrate a larger cache on a limited CPU area, the manufacturing process is more demanding.

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