A Layout Method of Antifuse Series Field Programmable Gate Array

Abstract

The invention discloses a layout method of an antifuse field programmable gate array, the method comprising: 1) creating a first layout including N line nets formed by connecting M units with horizontal line nets and vertical line nets; 2) Obtain the cost of the first layout; 3) select a part of the M units to move, and obtain the cost of the second layout according to the steps 1) and 2); 4) combine the cost of the second layout with the The cost comparison of the first layout, wherein, when the cost of the second layout is greater than the cost of the first layout, the first layout is retained; when the cost of the second layout is less than the cost of the first layout, the second layout is used to replace the first layout Layout; the layout is looped until at least M moves are performed to determine an optimal layout. The invention greatly improves the layout speed of the field programmable gate array of the antifuse series, and optimizes the layout result.

Description

A Layout Method of Antifuse Series Field Programmable Gate Array technical field The invention relates to the field of integrated circuits, in particular to a layout method of an antifuse series field programmable gate array. Background technique Field Programmable Gate Array (Field Programmable Gate Array, FPGA) is the product of further development on the basis of programmable devices such as PAL, GAL, and CPLD. It emerged as a semi-custom circuit in the field of application-specific integrated circuits (ASIC), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of the limited number of original programmable device gates. The FPGA chip layout is mainly aimed at the layout of the logic units on the chip (called CELL in the antifuse series, that is, units) and the connection relationship between them, so as to find a reasonable position for each logic unit. The three common FPGAs are SRAM, Flash, and antifuse FPGAs. The mainstr...

AI Technical Summary

Problems solved by technology

Due to the large difference in chip structure, the mainstream layout algorithm has obvious shortcomings such as low efficiency, unreasonable layout results, and high pressure on wiring in the application of antifuse series FPGAs.

The existing layout method is to find the layout result through steps such as initial layout, iteratively moving the logic unit, and checking the layout result. When this method is applied to the antifuse series FPGA chip, the iteration takes a long time, the calculation result is unreasonable, and the layout speed Slow, layout results are not ideal