Asynchronous cache method, asynchronous cache and integrated circuit

Abstract

The invention discloses an asynchronous cache method. Address blocks of a first asynchronous cache are coded according to coding of middle portion address blocks and the coding of virtual address blocks of a second asynchronous cache; the depth of the first asynchronous cache is any even number of address blocks which are smaller than the depth of the second asynchronous cache; the state of the first asynchronous cache is determined according to the address block coding indicated through a reading or writing pointer in the data reading and writing process. Meanwhile the invention also discloses the asynchronous cache and an integrated circuit. According to the asynchronous cache method, the asynchronous cache and the integrated circuit, the requirements for the depth of the asynchronous cache can be met, the more waste of the addressing space in the using process of the large depth of asynchronous cache is avoided, the structure is simple, the circuit implementation is easy, the size of the asynchronous cache is reduced as far as possible, and the miniaturization of equipment with the asynchronous cache is facilitated.

Description

technical field [0001] The invention relates to cache technology, in particular to an asynchronous cache method, an asynchronous cache and an integrated circuit. Background technique [0002] FIFO (First Input First Output) buffer is a first-in first-out data buffer. The first-in data is read from the FIFO buffer. Compared with RAM, there is no external read-write address line. It is relatively simple to use, but only Data can be written sequentially, and data can be read sequentially. It cannot be read or written to a specified address by the address line as in ordinary memory. [0003] FIFO buffers are generally used for data transmission between different clock domains. For example, one end of FIFO is AD data acquisition, and the other end is PCI bus. Then FIFO can be used as data buffer between two different clock domains. In addition, FIFO buffers can also be used for data interfaces of different widths. For example, MCU bit 8-bit data output, and DSP may be 16-bit dat...

AI Technical Summary

Problems solved by technology

In this way, the addressing space of the FIFO buffer will be wasted, and the occupied space of the FIFO b

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