Circuit and method performed by the circuit

Abstract

Example embodiments of the present invention provide accuracy enhancement techniques to improve the signal-to-noise ratio of an ADC. For example, a normal bit test and an additional bit test of a digital word from the most significant bit (MSB) to a predetermined least significant bit can be performed. The results of the normal bit and additional bit trials are combined to generate a digital output signal. The residual error is measured and then the digital output signal is adjusted based on said measured residual error.

Description

technical field [0001] The present invention relates to an analog-to-digital converter (analog-to-digital converter, referred to as ADC), in particular to a method for improving accuracy. Background technique [0002] An analog-to-digital converter converts an incoming analog signal into a digital representation (eg, a digital word). Successive Approximation Register ADC (SAR ADC for short), this ADC is through a series of most significant bit (Most-Significant Bit, referred to as MSB) to least significant bit (Least-Significant Bit, referred to as LSB) sequence Represents a bit of experimentation that implements the conversion of an analog signal into digital form. In each bit trial, the comparator compares the input analog signal with the reference voltage and decides whether the corresponding bit is "1" or "0" based on the comparator. Errors that occur during the conversion process are called SAR ADC conversion errors. Generally, the greater the conversion error, the w...

AI Technical Summary

Problems solved by technology

Traditional methods of reducing conversion error include using smaller bits to reduce quantization error or tuning components to reduce circuit noise, however, these methods are expensive in terms of speed, power, and / or circuit area

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