32results about "Conversion using stochastic techniques" patented technology

A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature.

The invention discloses an analog-digital converter circuit. The analog-digital converter circuit comprises a sub-ADC circuit and a sub-DAC circuit which are electrically connected, wherein the sub-ADC circuit comprises a plurality of comparators; the sub-DAC circuit comprises a plurality of DAC units; each comparator is corresponding to the corresponding DAC unit; the number of the comparators isthe same as the number of the DAC units; the analog-digital converter circuit further comprises a threshold voltage generating circuit; the threshold voltage generating circuit is used for generatingthreshold voltages of the plurality of comparators; the threshold voltage generating circuit comprises a dynamic element matching circuit; and the dynamic element matching circuit is used for connecting the outputs of the comparators and the inputs of the DAC units in a random sequence in a one-to-one mode. According to the analog-digital converter circuit provided by the invention, the data delay of the sub-ADC to the sub-DAC is greatly reduced, and the complexity of the circuit is greatly reduced.

A method and system for encoding an analog signal on a stochastic signal, the encoded signal then converted to a digital signal by an analog to digital converter, the analog to digital converter thereafter decoding from the encoded signal a digital signal, which corresponds to the analog signal. The stochastic signal may be a noise signal shaped to a Gaussian normal curve. An encoding process is performed by a multiplication circuit, which multiplies the stochastic signal by the analog signal, producing a product signal for an analog to digital conversion. During analog to digital conversion, the product signal is decoded. The decoding is performed using an arithmetic operation, which may be a Root Sum Square function or a Root Means Square function. The decoded signal is then mapped to account for offset error, gain error, and endpoint adjustment. The result is a decoded digital signal corresponding to the analog signal.

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits are configured to convert an input signal according to interleaved clock signals to generate first quantized outputs. The calibration circuit is configured to perform at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit further includes a first adjusting circuit. The first adjusting circuit is configured to analyze adjacent clock signals according to part of the second quantized outputs to generate adjusting information. The skew adjusting circuit is configured to analyze time difference information within even-numbered sampling periods of the clock signals according to the second quantized outputs and the adjusting information to generate adjustment signals. The adjustment signals are configured to reduce clock skews of the ADC circuits.

A digital slope analog to digital converter device includes a capacitor array circuit, a switching circuitry, comparator circuits, encoder circuitries, and a control logic circuit. The capacitor array circuit generates a first signal according to an input signal and switching signals. The switching circuitry generates the switching signals according to an enable signal and a first valid signal in the valid signals. Each of the comparator circuits compares the first signal with a predetermined voltage, in order to generate a corresponding one of the valid signals. Each of the encoder circuitries receives the switching signals according to a corresponding one of the valid signals, in order to generate a corresponding one of sets of first digital codes. The control logic circuit performs a statistics calculation according to the sets of first digital codes, in order to generate a second digital code.

The invention discloses a pipeline level operation device and a pipeline analog-to-digital converter. The pipeline level operation device comprises a dynamic matching sub-analog-to-digital converter, a sampling holder, a pseudo-random code generator and a multiplication digital-to-analog converter, wherein the multiplication digital-to-analog converter is respectively connected with the dynamic matching sub-analog-to-digital converter and the sampling holder, and the dynamic matching sub-analog-to-digital converter is connected with the pseudo-random code generator. Based on the dynamic matching sub-analog-to-digital converter, the threshold voltages of comparators can be changed by using pseudo-random codes, and the dynamic matching of the comparators is realized, so the dynamic matching of a capacitor array in the sub-analog-to-digital converter in the multiplication digital-to-analog converter is realized, and capacitor mismatching caused by process errors, manufacturing processes and the like is scattered. As the threshold voltages of the comparators only need to be prepared before comparison of the comparators, the dynamic matching technology of the threshold voltages can be applied to the retention period of the whole analog-to-digital conversion, and on the basis of not occupying the analog-to-digital conversion time, harmonic distortion is reduced and the linearity of the analog-to-digital converter is improved.

The invention discloses a random multiphase clock generation circuit, which comprises a random encoding module, an encoding queue module and a code-to-clock module, wherein the random encoding modulecomprises a first register, the encoding queue module comprises M-1 cascaded second registers, M sub-clock signals are correspondingly numbered, and the M numbers are encoded and serve as initial storage values of the first register and the M-1 second registers respectively; the encoding queue module is used for outputting the code stored in the last cascaded second register to the random encodingmodule and the code-to-clock module in each clock period of the main clock signal; the random encoding module is used for randomly selecting one code from the code stored in the first register and the code output by the encoding queue module and outputting the selected code to a cascaded first second register in the encoding queue module in each clock period of the main clock signal; and the code-to-clock module is used for outputting a sub-clock signal corresponding to the code output by the encoding queue module.

Systems and methods are provided for which a chopper modulator and a chopper demodulator of a chopped apparatus having a variable chopper frequency are described. A feedback path is used to reduce ripples and/or remaining offsets as a result of the variable chopper frequency.

A resonator device includes first and second resonators and an integrated circuit device. The integrated circuit device includes a first oscillation circuit configured to oscillate the first resonator, a second oscillation circuit configured to oscillate the second resonator, and a processing circuit configured to perform processing by using frequency difference information or frequency comparison information between a first clock signal generated by oscillating the first resonator and a second clock signal generated by oscillating the second resonator. The first resonator is supported on the integrated circuit device by a first support portion. The second resonator is supported on the integrated circuit device by a second support portion.