37results about "Conversion using stochastic techniques" patented technology

Apparatus for building a stochastic model of a time sequential data sequence, the data sequence comprising symbols selected from a finite symbol set, the apparatus comprising: an input for receiving said data sequence, a tree builder for expressing said symbols as a series of counters within nodes, each node having a counter for each symbol, each node having a position within said tree, said position expressing a symbol sequence and each counter indicating a number of its corresponding symbol which follows a symbol sequence of its respective node, and a tree reducer for reducing said tree to an irreducible set of conditional probabilities of relationships between symbols in said input data sequence. The tree may then be used to carry out a comparison with a new data sequence to determine a statistical distance between the old and the new data sequence.

Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logic modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

The invention discloses a stochastic time-digital converter, which comprises an input switching circuit, a stochastic time-digital converter (STDC) array and an encoder. A clock circuit inputs two clock signals into the two input ends of the input switching circuit respectively. The input switching circuit transmits the two clock signals input by the clock signal to the two input ends of the STDC array in form of alternate transposition, and simultaneously outputs a triggering control signal to the encoder. Each comparator in the STDC array independently judges the speed of each clock signal, and transmits a judgment result to the encoder for summarization. The encoder outputs the magnitude and plug-minus of a phase difference between the two clock signals. The number of equivalent comparators in the STDC array is multiplied by utilizing the stochastic characteristics of the STDC to maximally eliminate device mismatching and the influence of a process, power voltage and temperature on the circuit; and compared with the conventional STDC circuit, the STDC has the characteristics of hardware saving, low power consumption and small area.

Aspects of a method and system for a successive approximation analog-to-digital converter with dynamic search algorithms are provided. In some embodiments, a successive approximation analog-to-digital converter includes a digital-to-analog converter, a comparator, and a search and decode logice modules which cooperate to generate a digital output code representative of the analog input voltage based on a dynamic search algorithm. The dynamic search algorithms may alter a sequence of reference voltages used to successively approximate the analog input voltage based on one or more characteristics of the analog input voltage.

A distributive photonic monobit analog-to-digital converter includes a plurality of signal processing chains configured to receive a corresponding plurality of analog input electrical signals. Each processing chain includes an incoherent optical source configured to generate an optical noise signal, an optical modulator configured to modulate an analog input electrical signal of the plurality of analog input electrical signals onto an input optical signal to generate an optical modulated signal, a coupler configured to couple the optical modulated signal with the optical noise signal to generate a coupled signal, a photodetector configured to generate a phase difference between the optical modulated signal and the optical noise signal using the coupled signal, and a limiter configured to output a decision signal based on the phase difference and using a clock signal. A multi-phase clock generator is configured to generate the clock signal for each of the plurality of signal processing chains.

Random sequences are generated based on a stochastic generative model having multiple random variates. Inputs representative of the stochastic generative model are received. The inputs include a first random variate having a finite set of alphabets, a second random variate having a set of alphabets, and a third random variate having a finite set of alphabets. Outputs representative of the random sequences are generated based on the stochastic generative model. The outputs include a first random sequence that is a finite-length random sequence of alphabets randomly selected from the first random variate, a second random sequence having a set of alphabets selected from the second random variate, and a third random sequence having a set of alphabets randomly selected from the third random variate.

Systems and methods for flow sensing in a conduit are provided. One system includes a flow disturber disposed in a flow conduit and configured to impart a flow disturbance to the fluid flow. The system further includes a plurality of flow sensors disposed in the flow conduit and responsive to flow characteristics in the flow conduit. The system also includes a frequency resolver configured to determine frequency information related to the fluid flow based on the flow characteristics. The frequency resolver uses one or more time sample windows to select data samples for use in determining the frequency information, wherein a length of one or more of the time sample windows is based at least in part on the flow characteristics. The system additionally includes a processor configured to determine a flow rate of the fluid flow in the flow conduit using the frequency information.

A stochastic time-digital converter (STDC) including an input switching circuit, an STDC array, and an encoder. A clock circuit inputs two clock signals into two input terminals of the input switching circuit; the input switching circuit transmits the two clock signals in a cyclic cross-transposition form to two input terminals of the STDC array, and simultaneously outputs a trigger control signal to the encoder; each comparator in the STDC array independently judges the speeds of the two clock signals and sends the judgement results to the encoder for collection and processing; and the encoder outputs the size and positivity or negativity of the phase difference of the two clock signals. The technical solution utilizes the stochastic characteristic of the STDC to double the number of the equivalent comparators in the STDC array, eliminating the effects on the circuitry of device mismatching and processes, power supply voltage, and temperature.

The invention discloses an analog-digital converter circuit. The analog-digital converter circuit comprises a sub-ADC circuit and a sub-DAC circuit which are electrically connected, wherein the sub-ADC circuit comprises a plurality of comparators; the sub-DAC circuit comprises a plurality of DAC units; each comparator is corresponding to the corresponding DAC unit; the number of the comparators isthe same as the number of the DAC units; the analog-digital converter circuit further comprises a threshold voltage generating circuit; the threshold voltage generating circuit is used for generatingthreshold voltages of the plurality of comparators; the threshold voltage generating circuit comprises a dynamic element matching circuit; and the dynamic element matching circuit is used for connecting the outputs of the comparators and the inputs of the DAC units in a random sequence in a one-to-one mode. According to the analog-digital converter circuit provided by the invention, the data delay of the sub-ADC to the sub-DAC is greatly reduced, and the complexity of the circuit is greatly reduced.

A power supply margin controller may alter the voltage of a control signal used to control the output voltage of a power supply. The controller may include a digital-to-analog converter having an input and an output, and a comparator having a first input coupled to receive the control signal, a second input coupled to the output of the digital-to-analog converter, and an output. The controller may include a processing system configured to deliver data to the input of the digital-to-analog converter based on the output from the comparator that causes signals at the inputs to the comparator to be substantially equal.

A method and system for encoding an analog signal on a stochastic signal, the encoded signal then converted to a digital signal by an analog to digital converter, the analog to digital converter thereafter decoding from the encoded signal a digital signal, which corresponds to the analog signal. The stochastic signal may be a noise signal shaped to a Gaussian normal curve. An encoding process is performed by a multiplication circuit, which multiplies the stochastic signal by the analog signal, producing a product signal for an analog to digital conversion. During analog to digital conversion, the product signal is decoded. The decoding is performed using an arithmetic operation, which may be a Root Sum Square function or a Root Means Square function. The decoded signal is then mapped to account for offset error, gain error, and endpoint adjustment. The result is a decoded digital signal corresponding to the analog signal.

Described is a method for accurately reconstructing analog signals. The present invention considers a general parameter estimation problem, extends the utility of compressive sensing to real scenarios, and is able to accurately estimate center frequencies and amplitudes. Specifically, an unknown continuous analog signal comprising a set of arbitrary frequencies and amplitudes is received. A set of non-uniform samples of the unknown continuous analog signal is then obtained at multiple times. Finally, an iterative reconstruction process is utilized to determine a set of frequencies and a set of amplitudes that best fit the set of non-uniform samples in a global minimum problem in order to accurately reconstruct the continuous analog signal.

A method and system for encoding an analog signal on a stochastic signal, the encoded signal then converted to a digital signal by an analog to digital converter, the analog to digital converter thereafter decoding from the encoded signal a digital signal, which corresponds to the analog signal. The stochastic signal may be a noise signal shaped to a Gaussian normal curve. An encoding process is performed by a multiplication circuit, which multiplies the stochastic signal by the analog signal, producing a product signal for an analog to digital conversion. During analog to digital conversion, the product signal is decoded. The decoding is performed using an arithmetic operation, which may be a Root Sum Square function or a Root Means Square function. The decoded signal is then mapped to account for offset error, gain error, and endpoint adjustment. The result is a decoded digital signal corresponding to the analog signal.

An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits are configured to convert an input signal according to interleaved clock signals to generate first quantized outputs. The calibration circuit is configured to perform at least one calibration operation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit further includes a first adjusting circuit. The first adjusting circuit is configured to analyze adjacent clock signals according to part of the second quantized outputs to generate adjusting information. The skew adjusting circuit is configured to analyze time difference information within even-numbered sampling periods of the clock signals according to the second quantized outputs and the adjusting information to generate adjustment signals. The adjustment signals are configured to reduce clock skews of the ADC circuits.

A digital slope analog to digital converter device includes a capacitor array circuit, a switching circuitry, comparator circuits, encoder circuitries, and a control logic circuit. The capacitor array circuit generates a first signal according to an input signal and switching signals. The switching circuitry generates the switching signals according to an enable signal and a first valid signal in the valid signals. Each of the comparator circuits compares the first signal with a predetermined voltage, in order to generate a corresponding one of the valid signals. Each of the encoder circuitries receives the switching signals according to a corresponding one of the valid signals, in order to generate a corresponding one of sets of first digital codes. The control logic circuit performs a statistics calculation according to the sets of first digital codes, in order to generate a second digital code.

The application discloses a kind of pipeline operation device and pipeline analog-digital converter, comprising: dynamic matching sub-analog-digital converter, sample holder, pseudo-random code generator and multiplication digital-analog converter;Multiplication digital-analog converter is connected with dynamic matching sub-analog-digital converter and sample holder respectively, and dynamic matching sub-analog-digital converter is connected with pseudo-random code generator.Based on dynamic matching sub-analog-digital converter, using pseudo-random code can change the threshold voltage of comparator, realize the dynamic matching of comparator, so as to realize the dynamic matching of capacitor array in sub-analog-digital converter in multiplication digital-analog converter, and the capacitor mismatch caused by process error, manufacturing process etc.is scattered.Due to the threshold voltage of comparator only needs to be prepared before comparison, so the dynamic matching technology of threshold voltage can be used in the holding period of entire analog-digital conversion, on the basis of not squeezing analog-digital conversion time, reduce harmonic distortion, improve the linearity of analog-digital converter.

An ADC circuit (50) is disclosed. The ADC circuit (50) comprises a global input configured to receive an input voltage (Vin) and a plurality of converter circuits (105l-105N). Each converter circuit (105j) comprises a comparator circuit (70j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70j). Furthermore, each converter circuit (105j) comprises a one-bit current-output DAC (110j) having an input directly controlled from the output of the comparator circuit (70j) and an output connected to the second input of the comparator circuit (70j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits (70j).

Certain aspects of the present disclosure provide a probabilistic analog-to-digital converter (ADC). The probabilistic ADC can be configured to convert an analog input into a variable length or variable amplitude pulse, apply the pulse as a switching pulse to a plurality of memory elements, and store a value based on the memory element after the switching pulse is applied. The number of elements to determine the digital value.

A stochastic signal generation circuit includes a signal output circuit and a signal processing circuit connected with the signal output circuit. The signal output circuit includes two matching semiconductor components, wherein the signal output circuit detects a slight mismatch between the two matching semiconductor components, converts the detected slight mismatch into a corresponding electric signal, amplifies the electric signal, and outputs an analog voltage signal. The signal processing circuit converts the analog voltage signal into a stochastic digital signal. Also, a method for generating a stochastic signal is provided. The present invention decreases the cost of the integrated circuit, and better ensures the information security of the electronic products.

An ADC circuit (50) is disclosed. It comprises a global input configured to receive an input voltage (Vin) and a plurality of converter circuits (105l-105N). Each converter circuit (105j) comprises a comparator circuit (70j) having a first input connected to the global input, a second input, and an output configured to output a one-bit output signal of the comparator circuit (70j). Furthermore, each converter circuit (105j) comprises a one-bit current-output DAC (110j) having an input directly controlled from the output of the comparator circuit (70j) and an output connected to the second input of the comparator circuit (70j). The second inputs of all comparator circuits are interconnected. The ADC circuit (50) further comprises a digital output circuit (130) configured to generate an output signal z[n] of the ADC circuit (50) in response to the one-bit output signals of the comparator circuits (70j).

The invention discloses a pipeline level operation device and a pipeline analog-to-digital converter. The pipeline level operation device comprises a dynamic matching sub-analog-to-digital converter, a sampling holder, a pseudo-random code generator and a multiplication digital-to-analog converter, wherein the multiplication digital-to-analog converter is respectively connected with the dynamic matching sub-analog-to-digital converter and the sampling holder, and the dynamic matching sub-analog-to-digital converter is connected with the pseudo-random code generator. Based on the dynamic matching sub-analog-to-digital converter, the threshold voltages of comparators can be changed by using pseudo-random codes, and the dynamic matching of the comparators is realized, so the dynamic matching of a capacitor array in the sub-analog-to-digital converter in the multiplication digital-to-analog converter is realized, and capacitor mismatching caused by process errors, manufacturing processes and the like is scattered. As the threshold voltages of the comparators only need to be prepared before comparison of the comparators, the dynamic matching technology of the threshold voltages can be applied to the retention period of the whole analog-to-digital conversion, and on the basis of not occupying the analog-to-digital conversion time, harmonic distortion is reduced and the linearity of the analog-to-digital converter is improved.

The invention discloses a real-time processing method for dynamic signals of inertial sensors. Firstly, the random sampling technology is used to fully reduce the sampling data of the signal; The algorithm completes the accurate reconstruction of the original signal to improve the output accuracy of the dynamic signal of the inertial sensor. Compared with the traditional method, the invention can effectively improve the precision of the output signal while greatly reducing the sampling data of the signal, so as to realize the real-time processing of the dynamic signal of the inertial sensor.

The invention discloses a random multiphase clock generation circuit, which comprises a random encoding module, an encoding queue module and a code-to-clock module, wherein the random encoding modulecomprises a first register, the encoding queue module comprises M-1 cascaded second registers, M sub-clock signals are correspondingly numbered, and the M numbers are encoded and serve as initial storage values of the first register and the M-1 second registers respectively; the encoding queue module is used for outputting the code stored in the last cascaded second register to the random encodingmodule and the code-to-clock module in each clock period of the main clock signal; the random encoding module is used for randomly selecting one code from the code stored in the first register and the code output by the encoding queue module and outputting the selected code to a cascaded first second register in the encoding queue module in each clock period of the main clock signal; and the code-to-clock module is used for outputting a sub-clock signal corresponding to the code output by the encoding queue module.

The invention discloses a randomized channel calibration method and system based on pseudo-random codes , which are used for a multi-channel time domain interleaved analog-to-digital converter, and the method comprises the following steps of: adding delta M randomized channels outside M standard channels of the multi-channel time domain interleaved analog-to-digital converter to form M + delta M channels; generating a pseudo-random code for performing channel selection on the M + delta M channels; selecting M channels from the M + delta M channels as effective channels according to the pseudo-random code; and generating a sampling clock and a digital code output clock according to the selection result of the effective channel so as to control the selected effective channel to perform dataprocessing and output a digital code. The method and system are based on a pseudo-random code generation circuit, complete randomization of channels can be achieved under the condition that time is long enough, frequency spectrum stray of output signals can be effectively reduced, random gain errors and offset errors between the channels are effectively reduced, and the performance of the whole analog-digital converter is improved.

Systems and methods are provided for which a chopper modulator and a chopper demodulator of a chopped apparatus having a variable chopper frequency are described. A feedback path is used to reduce ripples and / or remaining offsets as a result of the variable chopper frequency.

The ADC includes an input, multiple quantizers, multiple feedback loops, and multiple filters. The input receives an input signal. The multiple quantizers include an Nth quantizer, which has an Nth quantizer input and an Nth quantizer output. The Nth quantizer input is connected to the input. A loop is formed around the Nth quantizer output and the Nth quantizer input and is configured to reduce the difference between the Nth quantizer output signal and the Nth reference signal in the Nth frequency domain. The multiple filters include an Nth filter. The Nth filter selects the Nth frequency domain. The feedback loop provides a means to control non-ideal effects such as comparator offset.