Analog-digital converter circuit

An analog-to-digital converter and circuit technology, applied in the field of integrated circuits, can solve problems such as delay increase, DAC unit gain inconsistency, circuit complexity, etc., and achieve the effects of reducing data delay, increasing sampling rate, and reducing complexity

Active Publication Date: 2018-03-16
SHANGHAI BEILING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0007] The technical problem to be solved by the present invention is to overcome the complexity of the circuit used by the analog-to-digital converter circuit in the prior art when solving the comparator offset voltage, the gain inconsistency between the DAC units inside the sub-DAC and the output error of the analog converter circuit, and Defects that introduce delay and increase chip area provide an analog-to-digital converter circuit that can reduce circuit complexity and increase circuit speed

Method used

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Embodiment Construction

[0039] The present invention is further illustrated below by means of examples, but the present invention is not limited to the scope of the examples.

[0040] Such as Figure 12 As shown, an analog-to-digital converter circuit includes an electrically connected sub-ADC circuit and a sub-DAC circuit, wherein the sub-ADC circuit includes four comparators, the sub-DAC circuit includes 4 DAC units, and the analog-to-digital converter The circuit also includes a threshold voltage generating circuit 1, which is used to generate the threshold voltage V of the four comparators TH ; the threshold voltage generation circuit 1 includes a dynamic element matching circuit 101 , a threshold jitter voltage injection circuit 102 and a comparator offset voltage calibration circuit 103 .

[0041] The dynamic element matching circuit 101 is used to connect the outputs of the four comparators one-to-one with the inputs of the four DAC units in random order. The dynamic element matching circuit...

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Abstract

The invention discloses an analog-digital converter circuit. The analog-digital converter circuit comprises a sub-ADC circuit and a sub-DAC circuit which are electrically connected, wherein the sub-ADC circuit comprises a plurality of comparators; the sub-DAC circuit comprises a plurality of DAC units; each comparator is corresponding to the corresponding DAC unit; the number of the comparators isthe same as the number of the DAC units; the analog-digital converter circuit further comprises a threshold voltage generating circuit; the threshold voltage generating circuit is used for generatingthreshold voltages of the plurality of comparators; the threshold voltage generating circuit comprises a dynamic element matching circuit; and the dynamic element matching circuit is used for connecting the outputs of the comparators and the inputs of the DAC units in a random sequence in a one-to-one mode. According to the analog-digital converter circuit provided by the invention, the data delay of the sub-ADC to the sub-DAC is greatly reduced, and the complexity of the circuit is greatly reduced.

Description

technical field [0001] The invention belongs to the technical field of integrated circuits, in particular to an analog-to-digital converter circuit. Background technique [0002] Analog-to-digital converters (ADC) are used to convert analog signals into digital signals, and are widely used in various data acquisition and communication systems. The sampling rate of the ADC directly determines the signal bandwidth that can be processed, and the accuracy of the ADC (such as the signal-to-noise ratio SNR, spurious-free dynamic range SFDR, etc.) determines the dynamic range of the entire system. ADC has a variety of architectures, such as pipelined ADC, successive approximation (SAR ADC), flash (flash ADC), time domain interleaved (interleavedADC) and so on. Among these architectures, the pipelined ADC can achieve relatively high precision and speed at the same time, so it is widely used. [0003] figure 1 The basic architecture of a pipelined ADC is given, the input signal V ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H03M1/04
CPCH03M1/04
Inventor 张辉富浩宇高远王海军
Owner SHANGHAI BEILING
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