Patents
Literature
Patsnap Eureka AI that helps you search prior art, draft patents, and assess FTO risks, powered by patent and scientific literature data.

3results about How to "High sampling rate" patented technology

Semi-passive air sampler

PendingCN122084332Ahigh sampling rateRealize zero power consumption operationWithdrawing sample devicesAir monitoringEnvironmental engineering
The invention belongs to the technical field of ambient air monitoring, and provides a semi-passive air sampler which comprises a main shell, a sampling pipe is detachably connected in the main shell, the sampling pipe is filled with a gaseous pollutant adsorbent, an air entraining head is arranged above the main shell, the air entraining head is communicated with the air inlet end of the sampling pipe, and the air entraining head is communicated with the air inlet end of the sampling pipe. A lifting assembly is arranged between the air entraining head part and the main shell; the auxiliary shell is detachably connected to the main shell through a buckling piece, an air outlet channel is formed in the auxiliary shell, one end of the air outlet channel is communicated with the air outlet end of the sampling pipe, the other end of the air outlet channel is vertically communicated with an air cylinder, a solar heating mechanism is arranged in the air cylinder, and the solar heating mechanism is used for heating air at the bottom of the air cylinder; and air in the air outlet duct is driven to flow into the air duct. Passive driving can be achieved through solar energy, semi-passive air collection is achieved, and meanwhile the sampling height can be flexibly adjusted.
Owner:LEXIN TESTING TECH CO LTD

Gate voltage bootstrap switching circuit for SAR ADC

The present invention discloses a gate voltage bootstrap switch circuit for a SAR ADC, which includes a voltage control unit and a switch transistor unit. The voltage control unit includes a first capacitor and a second capacitor connected in parallel. One end of each of the first capacitor and the second capacitor is connected to an external power supply, and the other end of each is connected to the switch transistor unit. The switch transistor unit includes a switch MOS transistor, a first MOS transistor, and a second MOS transistor. The gate of the switch MOS transistor is connected to the other ends of the first capacitor and the second capacitor. When the capacitors discharge, the gate voltage of the switch MOS transistor rises to twice the power supply voltage. The substrate of the switch MOS transistor is commonly connected to the drain of the first MOS transistor and the source of the second MOS transistor. The drain of the second MOS transistor is connected to the source of the switch MOS transistor, and its gate is connected to the gate of the switch MOS transistor. The gate voltage bootstrap switch circuit of the present invention prevents the leakage behavior of the switch MOS transistor, reduces the on-resistance of the switch MOS transistor, and accelerates the sampling rate of the SAR ADC.
Owner:IPGOAL MICROELECTRONICS (SICHUAN) CO LTD

An 8-bit ADC circuit with step-by-step multi-bit quantization

This invention belongs to the field of analog integrated circuit technology, specifically relating to an 8-bit ADC circuit with step-by-step multi-bit quantization; it includes: a SIG-DAC capacitor array receiving differential input signals VIP and VIN, connected to a first enable signal module and 5 comparators, used for successive approximation of the main signal; a REF-DAC capacitor array receiving differential input signals VREFP and VREFN, connected to a second enable signal module and 5 comparators, used to generate a threshold voltage; an asynchronous clock module connected to the second enable signal module, a latch array, and 5 comparators; the latch array consists of 17 latch circuits, and is also connected to the first enable signal module, 5 comparators, and 2 decoder modules connected in series; this invention increases the overall performance of the ADC without adding an extra clock phase, increases the ADC's tolerance to comparison errors, requires fewer total clock cycles, and simplifies the asynchronous clock module.
Owner:CHONGQING UNIV OF POSTS & TELECOMM +1