5results about How to "High sampling rate" patented technology

The invention discloses a noise reduction frequency multiplication sampling circuit and sampling method for a phase discrimination type sensor, and belongs to the technical field of electronic circuit phase measurement. The noise reduction frequency multiplication sampling circuit comprises an amplification circuit, a clamping circuit, a resonance circuit and a comparison circuit which are connected in sequence. The clamping circuit is used for carrying out clamping processing on the amplified sine alternating-current signal so as to shape the sine alternating-current signal into a trapezoidal signal, and the resonance circuit oscillates the trapezoidal signal to generate a high-frequency signal; the comparison circuit converts the high-frequency signal into a square wave signal. The signal frequency is effectively improved under the condition that the original signal frequency is not changed from the hardware level, the input signal is subjected to high-frequency change only by adjusting the values of the inductance and the capacitance of the resonance circuit, the frequency multiplication times are not influenced by the operational amplifier, and the purpose of high-frequency sampling of the low-frequency signal is achieved. And the signal is converted into a square wave signal through frequency multiplication, and data acquisition is carried out at a rising edge and a falling edge of the square wave signal, so that high-resolution sampling can be realized.

This invention belongs to the field of analog integrated circuit technology, specifically relating to an 8-bit ADC circuit with step-by-step multi-bit quantization; it includes: a SIG-DAC capacitor array receiving differential input signals VIP and VIN, connected to a first enable signal module and 5 comparators, used for successive approximation of the main signal; a REF-DAC capacitor array receiving differential input signals VREFP and VREFN, connected to a second enable signal module and 5 comparators, used to generate a threshold voltage; an asynchronous clock module connected to the second enable signal module, a latch array, and 5 comparators; the latch array consists of 17 latch circuits, and is also connected to the first enable signal module, 5 comparators, and 2 decoder modules connected in series; this invention increases the overall performance of the ADC without adding an extra clock phase, increases the ADC's tolerance to comparison errors, requires fewer total clock cycles, and simplifies the asynchronous clock module.

The invention belongs to the technical field of ambient air monitoring, and provides a semi-passive air sampler which comprises a main shell, a sampling pipe is detachably connected in the main shell, the sampling pipe is filled with a gaseous pollutant adsorbent, an air entraining head is arranged above the main shell, the air entraining head is communicated with the air inlet end of the sampling pipe, and the air entraining head is communicated with the air inlet end of the sampling pipe. A lifting assembly is arranged between the air entraining head part and the main shell; the auxiliary shell is detachably connected to the main shell through a buckling piece, an air outlet channel is formed in the auxiliary shell, one end of the air outlet channel is communicated with the air outlet end of the sampling pipe, the other end of the air outlet channel is vertically communicated with an air cylinder, a solar heating mechanism is arranged in the air cylinder, and the solar heating mechanism is used for heating air at the bottom of the air cylinder; and air in the air outlet duct is driven to flow into the air duct. Passive driving can be achieved through solar energy, semi-passive air collection is achieved, and meanwhile the sampling height can be flexibly adjusted.

The application relates to the technical field of chip circuits, in particular to a special chip ADC circuit for a retinal prosthesis, which comprises a sampling switch module, a capacitor array module, a dynamic comparator, a digital control logic module and a digital correction module; the capacitor array module comprises a P-end capacitor array and an N-end capacitor array, the P-end capacitor array comprises a plurality of first capacitors connected in parallel, and each first capacitor is connected with a first control switch; the N-end capacitor array comprises a plurality of second capacitors connected in parallel, and each second capacitor is connected with a second control switch; the same direction end of the dynamic comparator is connected with the end capacitor of the P-end capacitor array, and the reverse end of the dynamic comparator is connected with the end capacitor of the N-end capacitor array; the digital control logic module is connected with the output end of the dynamic comparator; and the digital correction module is connected with the output end of the digital control logic module. The ADC circuit provided by the application is used for converting a sensor analog signal into a digital signal and realizes low power consumption and high resolution.

The present invention discloses a gate voltage bootstrap switch circuit for a SAR ADC, which includes a voltage control unit and a switch transistor unit. The voltage control unit includes a first capacitor and a second capacitor connected in parallel. One end of each of the first capacitor and the second capacitor is connected to an external power supply, and the other end of each is connected to the switch transistor unit. The switch transistor unit includes a switch MOS transistor, a first MOS transistor, and a second MOS transistor. The gate of the switch MOS transistor is connected to the other ends of the first capacitor and the second capacitor. When the capacitors discharge, the gate voltage of the switch MOS transistor rises to twice the power supply voltage. The substrate of the switch MOS transistor is commonly connected to the drain of the first MOS transistor and the source of the second MOS transistor. The drain of the second MOS transistor is connected to the source of the switch MOS transistor, and its gate is connected to the gate of the switch MOS transistor. The gate voltage bootstrap switch circuit of the present invention prevents the leakage behavior of the switch MOS transistor, reduces the on-resistance of the switch MOS transistor, and accelerates the sampling rate of the SAR ADC.