Random multiphase clock generation circuit

Abstract

The invention discloses a random multiphase clock generation circuit, which comprises a random encoding module, an encoding queue module and a code-to-clock module, wherein the random encoding modulecomprises a first register, the encoding queue module comprises M-1 cascaded second registers, M sub-clock signals are correspondingly numbered, and the M numbers are encoded and serve as initial storage values of the first register and the M-1 second registers respectively; the encoding queue module is used for outputting the code stored in the last cascaded second register to the random encodingmodule and the code-to-clock module in each clock period of the main clock signal; the random encoding module is used for randomly selecting one code from the code stored in the first register and the code output by the encoding queue module and outputting the selected code to a cascaded first second register in the encoding queue module in each clock period of the main clock signal; and the code-to-clock module is used for outputting a sub-clock signal corresponding to the code output by the encoding queue module.

Description

technical field [0001] The invention belongs to the technical field of digital-analog hybrid integrated circuits, and relates to a clock generation circuit, in particular to a random multi-phase clock generation circuit. Background technique [0002] The development of communication technology puts forward higher requirements on the speed and precision of analog-to-digital converter (ADC). Time-interleaved ADC (TI-ADC) is a structure in which multiple analog-to-digital converters work in parallel. This structure does not require each sub-ADC to have a fast working speed, but In the state of time interleaving, the overall working speed of the system can be doubled. Theoretically, under the condition that the working speed of the sub-analog-to-digital converter remains constant, the more channels there are, the faster the overall speed will be. However, due to non-ideal factors such as sampling time mismatch and gain mismatch among different sub-ADCs, the overall dynamic per...

AI Technical Summary

Problems solved by technology

However, due to non-ideal factors such as sampling time mismatch and gain mismatch among different sub-ADCs, the overall dynamic performance of the ADC will be severely degraded

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