52 results about "Principal clock" patented technology

The invention discloses a key sensor short-time abnormal distribution drift detection method in a unit start-stop process, and belongs to the technical field of gas turbine power plant financial supervision and artificial intelligence, and the method comprises the steps: synchronously triggering multi-channel signal collection through a main clock, and achieving noise suppression and data pre-screening through the combination of first-order difference and threshold filtering; constructing a nonlinear weighted feature matrix, and fusing a time attenuation coefficient and a shafting acceleration factor to enhance the transient feature expression capability; generating a sensor association graph based on double-threshold determination of weighted Pearson's correlation coefficients and mutual information, and dividing stable subgroups by using an incremental label propagation algorithm; designing a double-layer Cluster-GCN model, aggregating subgroup internal characteristics in the first layer, introducing a fuel valve position-acceleration comparison gating mechanism in the second layer to correct a global edge weight, and generating a node embedding vector sensitive to working condition change; gaussian kernel density estimation and an instantaneous deviation index of embedding similarity are fused, and a historical sliding mean value and subgroup connectivity analysis are combined, so that sensor faults and working condition abrupt changes are distinguished.

The invention discloses a control circuit of a serial port transceiver circuit and a clock synchronization method, and belongs to the technical field of data communication. The circuit comprises a clock synchronization circuit and a register value generation circuit, wherein the output end of the register value generation circuit is connected with the first input end of a first selector in a transceiver circuit; the clock synchronization circuit outputs a reference clock rising edge according to the received slow reference clock; the register value generation circuit counts a main clock based on the rising edge of the reference clock and outputs a self-adaptive baud rate count value; the first selector selects the self-adaptive baud rate count value and a configuration signal of the register block and outputs a selection signal; and the transceiving module drives data transceiving with the register group according to the clock corresponding to the selection signal so as to adjust the main clock. According to the circuit, the influence of the deviation between the preset value and the actual value on the communication precision can be reduced under the condition that the main clock of the equipment is unstable.

The invention discloses a power modulation method and system for an all-solid-state power supply, and belongs to the technical field of pulse power. The method comprises the following steps: converting a target waveform into a multi-level discrete waveform, and segmenting the multi-level discrete waveform into a plurality of continuous sub-waveforms according to polarity; for each sub-waveform, identifying all level switching moments, obtaining a time-level number corresponding relation, and generating a corresponding switching action time sequence matrix; the row index of the switching action time sequence matrix corresponds to the level number, the odd-numbered columns store the turn-on time parameters of the switching devices under the corresponding level number, and the even-numbered columns store the turn-off time parameters of the corresponding switching devices; and converting the switching action time sequence matrix into period counting based on an FPGA main clock, and generating a corresponding driving pulse signal by the FPGA according to time sequence data so as to control a switching device in the all-solid-state power supply and carry out power modulation. High-real-time and high-precision control on the switch of the solid-state power supply is realized, and the effect of arbitrary waveform power modulation is realized.

The invention discloses a novel time synchronization method and system for multiple sensors in a train positioning system. The method comprises the following steps: triggering distribution of timestamps of an ultra-wideband module, a laser radar, an inertial measurement unit and a millimeter-wave radar according to a main clock; distance measurement time delay is obtained through distance measurement of the ultra-wideband module; and acquiring delay time between the ultra-wideband module, the laser radar, the inertial measurement unit and the millimeter-wave radar and the central processing unit. Further, estimating clock drift rates of the ultra-wideband module, the laser radar, the inertial measurement unit and the millimeter-wave radar based on the delay time, and dynamically supplementing the clock drift rates; when the environment changes or the system parameters change, the time synchronization state of the ultra-wideband module, the laser radar, the inertial measurement unit and the millimeter wave radar is dynamically maintained, the subsequent control of the clock drift rate is compatible, and the overall compatibility of the environment change or the system parameter change is realized. And the accuracy of time synchronization of the plurality of sensors in the novel train positioning system is ensured.

The application provides a slope signal generating circuit. The slope signal generating circuit comprises: a high-bit weight encoder, which is adapted to receive a main clock signal and generate a driving signal based on the main clock signal; a cascade level trigger, which is adapted to receive the driving signal and generate at least two high-bit weight switch signals under the driving of the driving signal and an inverse signal thereof; and a high-bit weight current steering unit, which comprises at least two high-bit weight current steers connected in parallel in sequence, each of which is adapted to receive one of the at least two high-bit weight switch signals in sequence and turn on or off based on the received one high-bit weight switch signal, so that the high-bit weight current steering unit outputs an increasing or decreasing current to generate a slope signal. By using the application, not only the inter-symbol interference is reduced, but also the complex circuit design is avoided, the occupied area is saved, the power consumption is reduced, and the cost is saved.

The application discloses a power modulation method and system of a full solid-state power supply, and belongs to the technical field of pulse power. The method comprises the following steps: converting a target waveform into a multi-level discrete waveform, and dividing the multi-level discrete waveform into a plurality of continuous sub-waveforms according to polarity; for each sub-waveform, identifying all level switching moments to obtain a time-level number corresponding relationship, and generating a corresponding switch action time sequence matrix; the row index of the switch action time sequence matrix corresponds to the level number, and the odd columns store the turn-on time parameters of the corresponding switch devices under the corresponding level number, and the even columns store the turn-off time parameters of the corresponding switch devices; the switch action time sequence matrix is converted into period counting based on the main clock of the FPGA, and the FPGA generates corresponding driving pulse signals according to the time sequence data, so as to control the switch devices in the full solid-state power supply and perform power modulation. The switch of the solid-state power supply is controlled with high real-time performance and high precision, and the effect of arbitrary waveform power modulation is realized.

Certain aspects of the present disclosure are directed towards an interleaved sampling circuit. The interleaved sampling circuit generally includes: a clock generator having an input coupled to a main clock node and having a plurality of non-overlapping clock output nodes; and a plurality of sampling circuits, each of the plurality of sampling circuits having a first clock input coupled to a respective one of the non-overlapping clock output nodes and a second clock input coupled to the main clock node.

The present application relates to a clock synchronization system. The system includes: at least one first device, the first device is configured to perform clock synchronization through a global positioning system and a time synchronization protocol; at least one second device, the second device is configured to perform clock synchronization through a time synchronization protocol; at least one of the first devices and at least one of the second devices are sequentially connected through a network interface, the first device performs clock synchronization through the global positioning system, and the second device connected to the first device uses the clock synchronized by the first device as the main clock source; when at least one second device is connected to the second device, each of the second devices uses the clock synchronized by the previous second device as the main clock source for clock synchronization until the clock synchronization of all the second devices is completed. This system can realize a high-precision clock synchronization method for devices step by step.

The invention relates to the technical field of integrated circuits, and discloses a high-speed clock delay controller, system and control method.The controller is characterized in that a low-frequency pulse generation circuit receives a high-speed main clock signal and converts the high-speed main clock signal into low-frequency pulse signals with the number corresponding to the preset delay period number; the clock synchronization circuit is used for synchronizing the low-frequency pulse signal with a high-speed main clock signal and outputting a synchronization pulse signal; the clock pause control circuit is used for shortening the pulse width of the synchronous pulse signal to a high-speed main clock period and then negating to generate a clock pause control signal; the high-speed clock driving circuit is used for controlling pause or output of the high-speed main clock signal according to the clock pause control signal, integer period delay of the high-speed main clock signal is achieved, and a high-speed main clock delay signal is obtained. According to the invention, accurate and additional noise-free adjustable delay can be provided for a high-speed clock signal.

The application discloses a correction circuit and a correction method of a two-step multi-phase clock time-to-digital converter. The correction circuit comprises a selection module and a correction module. The selection module selects a corresponding correct clock signal based on the main clock level state in which the fine quantization signal flip edge is located. The selection module inputs the correct clock signal into the correction module. The correction module receives the correct clock signal for correction and generates two groups of digital calibration control codes. The digital calibration control codes are used for correcting the coarse quantization count value of a coarse quantization module. The correction operation comprises keeping, adding one, adding two, subtracting one or subtracting two operations on the coarse quantization count value. The correction method of the application is based on the above-mentioned correction circuit. The application solves the error caused by the metastability and transmission delay mismatch of the D flip-flop in the prior art, and realizes the correction of the metastability error and the transmission delay mismatch error of the D flip-flop.

The invention relates to the technical field of integrated circuits, and discloses an oscillator calibration circuit, a calibration method, an oscillator and electronic equipment, the circuit comprises a voltage-controlled oscillator, a clock processing module, an error amplification module, an open-loop control module and a calibration module, the voltage-controlled oscillator generates a main clock signal; the clock processing module performs frequency division processing on the main clock signal to generate a calibration starting signal and a conversion clock signal; the error amplification module outputs an amplified error voltage signal of the detection port; the open-loop control module makes the error amplification module enter an open-loop working mode in response to the effective state of the calibration starting signal; the calibration module responds to the conversion clock signal, applies bit-by-bit calibration excitation to the error amplification module by adopting a successive approximation mode from a preset initial calibration code, detects the polarity change of an error voltage signal of the error amplification module relative to an input short-circuit state, generates a target digital calibration code, and outputs the target digital calibration code; and compensating the error amplification module based on the target digital calibration code.

The invention relates to the technical field of signal processing, and discloses a clock control system and method.A first clock module and a second clock module have the same structure; the input end of the phase discriminator is connected with the first clock module and the second clock module, the output end of the phase discriminator is connected with the controller, and the phase discriminator compares and determines the phase difference of clock signals output by the first clock module and the second clock module and feeds back the phase difference to the controller; the controller is connected with the first clock module and the second clock module, and outputs an adjustment signal to the first clock module or the second clock module based on the phase difference; and the combiner is connected with the first clock module and the second clock module, and combines and outputs clock signals output by the first clock module and the second clock module. Self-calibration is achieved through the main clock link and the compensation clock link, the phase difference of clock signals of the main clock link and the compensation clock link is reduced, interference of the external environment is eliminated, and therefore phase noise is reduced, and stability is improved.

A communication circuit for reducing recoil noise of an eye open monitor comprises a first sampler, a second sampler and a pre-amplifier, the first output end and the second output end of the pre-amplifier are connected with the first input end and the second input end of the first sampler respectively, and the first input end and the second input end of the second sampler are connected with the first output end and the second output end of the pre-amplifier respectively. An input signal is applied to the preamplifier and a first input of the second sampler, respectively, and when an edge of the sub-clock precedes an edge of the master clock, the first sampler samples a data value by comparing the input signal with a second reference voltage at the edge of the sub-clock, the second sampler samples a data value by comparing the input signal with a first reference voltage at an edge of the master clock, and when an edge of the sub-clock lags the edge of the master clock, the second sampler samples a data value by comparing the input signal with a second reference voltage at an edge of the sub-clock, a first sampler samples a data value by comparing an input signal to a first reference voltage at an edge of a master clock.

The embodiment of the invention relates to an NFC tactile interaction display method and system supporting real-time query of a building material technology, and belongs to the technical field of electronic data processing. Reading building material identification data, obtaining a corresponding tactile waveform file, building material virtual model data and audio and video content from a server, establishing a main clock reference based on a zero buffer timestamp of an audio system, mapping process node time in a tactile waveform to the main clock reference, generating a node trigger queue, and sending the node trigger queue to the server; and comparing a moment difference value between a current clock and a trigger queue in real time through audio clock callback, generating synchronous touch, calculating a spatial position and an attitude matrix of the virtual model, and superposing the model into a real-time video stream to realize augmented reality display. According to the embodiment of the invention, through multi-modal data fusion and high-precision time sequence synchronization, immersive building material process display experience with integration of audiovisual and tactile sense is realized.

A clock grid structure design method for a two-level clock spine comprises: constructing a first-level master clock spine structure in a grid clock usage area; wherein the area includes multiple grid clock domain timing devices; the first-level master clock spine structure includes a balancing tree and a master clock spine line driven by it, the master clock spine line extending as a whole along a first direction and running through the entire grid clock usage area; constructing a second-level slave clock spine structure group; the second-level slave clock spine structure group includes a plurality of second-level slave clock spine structures, the second-level slave clock spine structure includes a balancing tree and a slave clock spine line driven by it, the slave clock spine lines being generally perpendicular to the first direction; short-circuiting the second-level slave clock spine structure group via multiple metal short-circuit lines to form a clock grid structure; the clock grid structure of the present invention is simple to implement, occupies less layout and wiring resources, and has low power consumption, while also having the advantages of strong chip layout adaptability and good scalability.

The invention discloses a time synchronization method and a related device, and relates to the field of control systems, and the method comprises the steps: configuring a time reference manager with high precision, comparing the manager time obtained by the time reference manager with the clock source time obtained by a main clock source during the time synchronization, and determining the time reference manager; when the manager time is determined to be slower than the clock source time according to the comparison result, the value of the manager time in the time reference manager is updated to be the clock source time, so that the controller performs related control and signal calibration based on the updated clock source time, and the requirement of the controller for higher time precision is met.

The invention discloses a communication method, a communication device, communication equipment and a computer readable storage medium, which are applied to the field of serial communication, and comprise the following steps of: adding a wakeup prefix sequence in front of a current data frame and adding a calibration pulse sequence behind the current data frame through a sending end to obtain a processed data frame; sending the processed data frame through an asynchronous communication line; when a low-power-consumption edge detection circuit of the receiving end identifies a wake-up prefix sequence on an asynchronous communication line, activating a main clock of the receiving end, and sampling effective data in a processed data frame corresponding to a current data frame based on an initial sampling point position or a sampling point position after last dynamic calibration; and when the sampling is completed, receiving and measuring the actual duration of the calibration pulse sequence through a receiving end, calculating clock skew according to the actual duration and the ideal duration, and adjusting the sampling point position of the next data frame based on the clock skew. According to the invention, the problems of asynchronous communication clocks and high power consumption are solved.

Embodiments of the present application disclose a method, apparatus, device, and storage medium for obtaining a clock constraint file. The method includes: obtaining the clock architecture of a chip; wherein, the clock architecture includes multiple clock layers, and each of the clock layers includes at least one clock unit; sequentially obtaining the clock definitions of each of the clock layers according to the layer sequence of the clock architecture; and obtaining a clock constraint file according to the clock definitions of each of the clock layers. The technical solution provided by the embodiments of the present application uses the clock definitions of all the clock layers whose layer sequences are before the current clock layer as the main clock of the current clock layer, sequentially obtains the clock definitions of each clock layer, and then obtains a clock constraint file according to the clock definitions of each clock layer, realizing the automatic generation of the clock constraint file, saving the writing time, improving the development efficiency, shortening the R & D cycle of the chip, and at the same time, improving the accuracy and reliability of the writing of the clock constraint file.

The invention discloses a clock source switching method and device, electronic equipment and a storage medium, and relates to the technical field of computers.Clock source nodes to be tested in a normal connection state are selected firstly, then performance testing is conducted on the clock source nodes to be tested, and multiple priority evaluation indexes of the clock source nodes to be tested are obtained; determining a performance comprehensive evaluation index of each to-be-tested clock source node according to the plurality of priority evaluation indexes, and sorting the performance comprehensive evaluation indexes to obtain a standby clock source priority list; according to the method, the to-be-tested clock source node with the highest priority can be selected as the new main clock source node according to the standby clock source priority list, so that the technical problem that the selected standby clock source may not be the optimal standby clock source due to the fact that the priority of each standby clock source in the predefined priority list is fixed is solved; and the accuracy of the standby clock source selection result and the reliability of the distributed storage system are improved.

The present disclosure provides a method for achieving synchronization in a Packet- Optical Transport Platform when primary and secondary clock inputs are out of sync. The method comprises periodically sampling (202) the clock inputs using a high-frequency sampling clock. When the primary clock input is unavailable, the method comprises determining (204) the phase difference (β) between the clock inputs based on the previously known phase of the primary clock input, and generating (206) an internal clock with the same frequency and phase as the primary clock input using the high-frequency clock input. Further, the method comprises shifting (208) the internally generated clock with each clock cycle until it aligns with a phase that ensures the phase difference between the internally generated clock and the secondary clock input falls within a predetermined limit, and initiating (210) a switch- over to the secondary clock input, thereby ensuring uninterrupted operation during clock transitions.

A phase synchronization system for a triple modular redundancy controller, comprising three controllers which communicate with each other, wherein each controller comprises an MCU and an FPGA; the FPGA is used for outputting a constant clock signal and diagnosing clock signals of all three controllers, the MCU periodically sends diagnosis data and phase data to the other two controllers by means of a communication module, and a voting synchronization module of the MCU votes and determines a main clock on the basis of the diagnosis data, and calculates a phase adjustment value on the basis of the phase data to complete phase synchronization with the main clock. The phase synchronization system for the triple modular redundancy controller has the characteristics of simple scheme and strong fault-tolerant capability.

The invention relates to the technical field of communication, in particular to an interface channel rate adaptation method and system and a computer program product, and the method comprises the steps: generating a token of a corresponding channel in a clock domain of each channel according to channel flow; synchronizing tokens of all channels to a main clock domain; and scheduling the flow of each channel in the main clock domain according to the token accumulation number of each channel to realize rate adaptation of all channels. According to the method, the token of the corresponding channel is generated in the clock domain of each channel based on the channel flow, the tokens of all the channels are synchronized to the main clock domain through the asynchronous fifo, the flow of each channel is scheduled in the main clock domain according to the accumulated number of the tokens of each channel, and rate adaptation of all the channels is achieved.

The invention relates to the technical field of electrical parameter measurement, and discloses a ring main unit multi-loop electrical parameter combined measurement and anomaly positioning method. The method is used for solving the problem that a unified time reference and channel-level synchronization mechanism is lacked in the collection process in a traditional method. The method comprises the following steps: firstly, by solidifying the configuration of a ring main unit loop and a sampling channel and generating a configuration verification identifier, establishing a main clock monotone increasing timing reference and consistently distributing a unified time mark number; a channel compensation gear is determined and solidified through calibration excitation, and a combined measurement frame with a data quality field is constructed and cached according to a time mark number in an operation period; after an event is triggered, according to an event starting point identifier and an event relative sequence number alignment frame segment, abnormal loop positioning information with an evidence range is output under consistency constraint and direction criteria, and cross-loop joint quantity stabilization and positioning result rechecking are achieved.

The invention discloses a laboratory constant-illumination-intensity sunlight illumination management system, belongs to the technical field of illumination management, and solves the problems that an ADC sampling clock of an irradiance feedback signal is modulated by switching noise and picosecond-level random jitter is generated, so that the phase collapse of a control loop is caused by ADC sampling jitter; and the problem that the service life of the lamp is shortened due to high-frequency self-oscillation caused by misjudgment of the phase of the digital PID controller and acceleration of lamp electrode sputtering is solved. According to the invention, an ultra-stable 156.25 MHz main clock signal is generated and is differentiated into four paths of 90-degree phase difference sampling clocks to drive a time-interleaved ADC array to execute anti-jitter four-phase sampling, clock jitter parameters are quantified in real time, a future jitter trend is predicted, and a compensation voltage is output to a phase modulation compensation module to generate an anti-phase correction signal to be injected into a compensation node of a clock distribution network; and finally, the digital correction engine executes complex exponential weighted average and finite impulse response filtering processing on the four-channel sampling data, outputs a control signal with small fluctuation, and recovers the service life of the xenon lamp.

The present application relates to the technical field of optical fiber Ethernet clock synchronization, in particular to a kind of optical fiber Ethernet multi-node clock synchronization control method and system.For the frame start delimiter in multistage optical fiber Ethernet link is transferred to the position deviating from the predetermined count position after reaching, the number of idle code groups under different port clock domain is not easy to match, main clock node sends reserved idle code group before synchronization frame and issues periodic serial number, main clock sends count value and the predetermined count position of each level node, relay node detects frame start delimiter and then latches arrival count value, determines the number of idle code groups to be increased or to be reduced according to difference value and the count length corresponding to single idle code group, adjusts the number of idle code groups before synchronization frame before forwarding, and the slave node determines output count position and generates second pulse or sampling trigger signal accordingly, thereby improving the consistency of multi-node synchronization output.

A method and system are provided for controlling clock operation in a memory that applies a test mode to test functionality of the memory which controls timing in a self-time loop using an external clock that on a rising edge triggers a main clock and on a falling edge provides a reset timer return path to reset the main clock signal. In the reset timer return path, a rising edge of the external clock triggers start of a self-time loop, and the rising edge of the external clock also controls the reset timer return path to block generation of a reference bit line (RBL) signal. In the reset timer return path, a falling edge of the external clock generates the RBL signal to provide an external clock return signal to enable an end of cycle for the self-time loop.

The invention relates to the field of FPGA (field programmable gate array) technology, and discloses a clock tree delay matching method, device and equipment and a storage medium, the method is applied to an FPGA system comprising a main clock tree and a copy path, and the programmable bit setting of a clock tree architecture and a clock switching center of the copy path is consistent with that of the main clock tree. Comprising the following steps: dynamically synchronizing SWH configuration of a main clock tree and a copy path by constructing the copy path which has the same clock tree architecture as the main clock tree and has a programmable bit of a clock switching center, so that the transmission delay of the copy path is matched with the delay change of the main clock tree in real time; a feedback clock signal generated by the copy path is compared with a reference clock signal in phase, a delay line is controlled by adjusting the voltage of the main clock tree, and automatic delay alignment of the main clock tree and the data path is achieved. Through cooperative configuration of a copy path and a main clock tree, the problem of phase mismatching of a clock signal and a data path caused by application configuration difference in a traditional FPGA is solved.

This invention relates to the field of signal processing technology and discloses a clock control system and method. In this invention, the first clock module and the second clock module have the same structure. The input terminal of a phase detector is connected to both the first and second clock modules, and the output terminal is connected to a controller. The phase detector compares and determines the phase difference between the clock signals output by the first and second clock modules and feeds it back to the controller. The controller is connected to both the first and second clock modules and outputs an adjustment signal to either the first or second clock module based on the phase difference. A combiner is connected to both the first and second clock modules and combines the clock signals output by the first and second clock modules before outputting the result. Self-calibration is achieved through the main clock link and the compensation clock link, reducing the phase difference between the clock signals of the main clock link and the compensation clock link, eliminating interference from the external environment, thereby reducing phase noise and improving stability.

In some embodiments, a system includes a plurality of compute nodes, clock connections to connect at least some of the compute nodes and to distribute a master clock among the at least some compute nodes, and processing circuitry to discover a clock distribution topology formed by the compute nodes and the clock connections.

Certain aspects of the present disclosure are directed towards an interleaved sampling circuit. The interleaved sampling circuit generally includes: a clock generator having an input coupled to a main clock node and having a plurality of non-overlapping clock output nodes; and a plurality of sampling circuits, each of the plurality of sampling circuits having a first clock input coupled to a respective one of the non-overlapping clock output nodes and a second clock input coupled to the main clock node.