34 results about "Principal clock" patented technology

The invention discloses a key sensor short-time abnormal distribution drift detection method in a unit start-stop process, and belongs to the technical field of gas turbine power plant financial supervision and artificial intelligence, and the method comprises the steps: synchronously triggering multi-channel signal collection through a main clock, and achieving noise suppression and data pre-screening through the combination of first-order difference and threshold filtering; constructing a nonlinear weighted feature matrix, and fusing a time attenuation coefficient and a shafting acceleration factor to enhance the transient feature expression capability; generating a sensor association graph based on double-threshold determination of weighted Pearson's correlation coefficients and mutual information, and dividing stable subgroups by using an incremental label propagation algorithm; designing a double-layer Cluster-GCN model, aggregating subgroup internal characteristics in the first layer, introducing a fuel valve position-acceleration comparison gating mechanism in the second layer to correct a global edge weight, and generating a node embedding vector sensitive to working condition change; gaussian kernel density estimation and an instantaneous deviation index of embedding similarity are fused, and a historical sliding mean value and subgroup connectivity analysis are combined, so that sensor faults and working condition abrupt changes are distinguished.

The invention discloses a power modulation method and system for an all-solid-state power supply, and belongs to the technical field of pulse power. The method comprises the following steps: converting a target waveform into a multi-level discrete waveform, and segmenting the multi-level discrete waveform into a plurality of continuous sub-waveforms according to polarity; for each sub-waveform, identifying all level switching moments, obtaining a time-level number corresponding relation, and generating a corresponding switching action time sequence matrix; the row index of the switching action time sequence matrix corresponds to the level number, the odd-numbered columns store the turn-on time parameters of the switching devices under the corresponding level number, and the even-numbered columns store the turn-off time parameters of the corresponding switching devices; and converting the switching action time sequence matrix into period counting based on an FPGA main clock, and generating a corresponding driving pulse signal by the FPGA according to time sequence data so as to control a switching device in the all-solid-state power supply and carry out power modulation. High-real-time and high-precision control on the switch of the solid-state power supply is realized, and the effect of arbitrary waveform power modulation is realized.

The application provides a slope signal generating circuit. The slope signal generating circuit comprises: a high-bit weight encoder, which is adapted to receive a main clock signal and generate a driving signal based on the main clock signal; a cascade level trigger, which is adapted to receive the driving signal and generate at least two high-bit weight switch signals under the driving of the driving signal and an inverse signal thereof; and a high-bit weight current steering unit, which comprises at least two high-bit weight current steers connected in parallel in sequence, each of which is adapted to receive one of the at least two high-bit weight switch signals in sequence and turn on or off based on the received one high-bit weight switch signal, so that the high-bit weight current steering unit outputs an increasing or decreasing current to generate a slope signal. By using the application, not only the inter-symbol interference is reduced, but also the complex circuit design is avoided, the occupied area is saved, the power consumption is reduced, and the cost is saved.

The application discloses a power modulation method and system of a full solid-state power supply, and belongs to the technical field of pulse power. The method comprises the following steps: converting a target waveform into a multi-level discrete waveform, and dividing the multi-level discrete waveform into a plurality of continuous sub-waveforms according to polarity; for each sub-waveform, identifying all level switching moments to obtain a time-level number corresponding relationship, and generating a corresponding switch action time sequence matrix; the row index of the switch action time sequence matrix corresponds to the level number, and the odd columns store the turn-on time parameters of the corresponding switch devices under the corresponding level number, and the even columns store the turn-off time parameters of the corresponding switch devices; the switch action time sequence matrix is converted into period counting based on the main clock of the FPGA, and the FPGA generates corresponding driving pulse signals according to the time sequence data, so as to control the switch devices in the full solid-state power supply and perform power modulation. The switch of the solid-state power supply is controlled with high real-time performance and high precision, and the effect of arbitrary waveform power modulation is realized.

Certain aspects of the present disclosure are directed towards an interleaved sampling circuit. The interleaved sampling circuit generally includes: a clock generator having an input coupled to a main clock node and having a plurality of non-overlapping clock output nodes; and a plurality of sampling circuits, each of the plurality of sampling circuits having a first clock input coupled to a respective one of the non-overlapping clock output nodes and a second clock input coupled to the main clock node.

The invention relates to the technical field of integrated circuits, and discloses a high-speed clock delay controller, system and control method.The controller is characterized in that a low-frequency pulse generation circuit receives a high-speed main clock signal and converts the high-speed main clock signal into low-frequency pulse signals with the number corresponding to the preset delay period number; the clock synchronization circuit is used for synchronizing the low-frequency pulse signal with a high-speed main clock signal and outputting a synchronization pulse signal; the clock pause control circuit is used for shortening the pulse width of the synchronous pulse signal to a high-speed main clock period and then negating to generate a clock pause control signal; the high-speed clock driving circuit is used for controlling pause or output of the high-speed main clock signal according to the clock pause control signal, integer period delay of the high-speed main clock signal is achieved, and a high-speed main clock delay signal is obtained. According to the invention, accurate and additional noise-free adjustable delay can be provided for a high-speed clock signal.

The application discloses a correction circuit and a correction method of a two-step multi-phase clock time-to-digital converter. The correction circuit comprises a selection module and a correction module. The selection module selects a corresponding correct clock signal based on the main clock level state in which the fine quantization signal flip edge is located. The selection module inputs the correct clock signal into the correction module. The correction module receives the correct clock signal for correction and generates two groups of digital calibration control codes. The digital calibration control codes are used for correcting the coarse quantization count value of a coarse quantization module. The correction operation comprises keeping, adding one, adding two, subtracting one or subtracting two operations on the coarse quantization count value. The correction method of the application is based on the above-mentioned correction circuit. The application solves the error caused by the metastability and transmission delay mismatch of the D flip-flop in the prior art, and realizes the correction of the metastability error and the transmission delay mismatch error of the D flip-flop.

The invention relates to the technical field of integrated circuits, and discloses an oscillator calibration circuit, a calibration method, an oscillator and electronic equipment, the circuit comprises a voltage-controlled oscillator, a clock processing module, an error amplification module, an open-loop control module and a calibration module, the voltage-controlled oscillator generates a main clock signal; the clock processing module performs frequency division processing on the main clock signal to generate a calibration starting signal and a conversion clock signal; the error amplification module outputs an amplified error voltage signal of the detection port; the open-loop control module makes the error amplification module enter an open-loop working mode in response to the effective state of the calibration starting signal; the calibration module responds to the conversion clock signal, applies bit-by-bit calibration excitation to the error amplification module by adopting a successive approximation mode from a preset initial calibration code, detects the polarity change of an error voltage signal of the error amplification module relative to an input short-circuit state, generates a target digital calibration code, and outputs the target digital calibration code; and compensating the error amplification module based on the target digital calibration code.

The invention relates to the technical field of signal processing, and discloses a clock control system and method.A first clock module and a second clock module have the same structure; the input end of the phase discriminator is connected with the first clock module and the second clock module, the output end of the phase discriminator is connected with the controller, and the phase discriminator compares and determines the phase difference of clock signals output by the first clock module and the second clock module and feeds back the phase difference to the controller; the controller is connected with the first clock module and the second clock module, and outputs an adjustment signal to the first clock module or the second clock module based on the phase difference; and the combiner is connected with the first clock module and the second clock module, and combines and outputs clock signals output by the first clock module and the second clock module. Self-calibration is achieved through the main clock link and the compensation clock link, the phase difference of clock signals of the main clock link and the compensation clock link is reduced, interference of the external environment is eliminated, and therefore phase noise is reduced, and stability is improved.

A communication circuit for reducing recoil noise of an eye open monitor comprises a first sampler, a second sampler and a pre-amplifier, the first output end and the second output end of the pre-amplifier are connected with the first input end and the second input end of the first sampler respectively, and the first input end and the second input end of the second sampler are connected with the first output end and the second output end of the pre-amplifier respectively. An input signal is applied to the preamplifier and a first input of the second sampler, respectively, and when an edge of the sub-clock precedes an edge of the master clock, the first sampler samples a data value by comparing the input signal with a second reference voltage at the edge of the sub-clock, the second sampler samples a data value by comparing the input signal with a first reference voltage at an edge of the master clock, and when an edge of the sub-clock lags the edge of the master clock, the second sampler samples a data value by comparing the input signal with a second reference voltage at an edge of the sub-clock, a first sampler samples a data value by comparing an input signal to a first reference voltage at an edge of a master clock.

The embodiment of the invention relates to an NFC tactile interaction display method and system supporting real-time query of a building material technology, and belongs to the technical field of electronic data processing. Reading building material identification data, obtaining a corresponding tactile waveform file, building material virtual model data and audio and video content from a server, establishing a main clock reference based on a zero buffer timestamp of an audio system, mapping process node time in a tactile waveform to the main clock reference, generating a node trigger queue, and sending the node trigger queue to the server; and comparing a moment difference value between a current clock and a trigger queue in real time through audio clock callback, generating synchronous touch, calculating a spatial position and an attitude matrix of the virtual model, and superposing the model into a real-time video stream to realize augmented reality display. According to the embodiment of the invention, through multi-modal data fusion and high-precision time sequence synchronization, immersive building material process display experience with integration of audiovisual and tactile sense is realized.

The invention discloses a time synchronization method and a related device, and relates to the field of control systems, and the method comprises the steps: configuring a time reference manager with high precision, comparing the manager time obtained by the time reference manager with the clock source time obtained by a main clock source during the time synchronization, and determining the time reference manager; when the manager time is determined to be slower than the clock source time according to the comparison result, the value of the manager time in the time reference manager is updated to be the clock source time, so that the controller performs related control and signal calibration based on the updated clock source time, and the requirement of the controller for higher time precision is met.

The invention discloses a communication method, a communication device, communication equipment and a computer readable storage medium, which are applied to the field of serial communication, and comprise the following steps of: adding a wakeup prefix sequence in front of a current data frame and adding a calibration pulse sequence behind the current data frame through a sending end to obtain a processed data frame; sending the processed data frame through an asynchronous communication line; when a low-power-consumption edge detection circuit of the receiving end identifies a wake-up prefix sequence on an asynchronous communication line, activating a main clock of the receiving end, and sampling effective data in a processed data frame corresponding to a current data frame based on an initial sampling point position or a sampling point position after last dynamic calibration; and when the sampling is completed, receiving and measuring the actual duration of the calibration pulse sequence through a receiving end, calculating clock skew according to the actual duration and the ideal duration, and adjusting the sampling point position of the next data frame based on the clock skew. According to the invention, the problems of asynchronous communication clocks and high power consumption are solved.

The invention discloses a clock source switching method and device, electronic equipment and a storage medium, and relates to the technical field of computers.Clock source nodes to be tested in a normal connection state are selected firstly, then performance testing is conducted on the clock source nodes to be tested, and multiple priority evaluation indexes of the clock source nodes to be tested are obtained; determining a performance comprehensive evaluation index of each to-be-tested clock source node according to the plurality of priority evaluation indexes, and sorting the performance comprehensive evaluation indexes to obtain a standby clock source priority list; according to the method, the to-be-tested clock source node with the highest priority can be selected as the new main clock source node according to the standby clock source priority list, so that the technical problem that the selected standby clock source may not be the optimal standby clock source due to the fact that the priority of each standby clock source in the predefined priority list is fixed is solved; and the accuracy of the standby clock source selection result and the reliability of the distributed storage system are improved.

The invention relates to the technical field of communication, in particular to an interface channel rate adaptation method and system and a computer program product, and the method comprises the steps: generating a token of a corresponding channel in a clock domain of each channel according to channel flow; synchronizing tokens of all channels to a main clock domain; and scheduling the flow of each channel in the main clock domain according to the token accumulation number of each channel to realize rate adaptation of all channels. According to the method, the token of the corresponding channel is generated in the clock domain of each channel based on the channel flow, the tokens of all the channels are synchronized to the main clock domain through the asynchronous fifo, the flow of each channel is scheduled in the main clock domain according to the accumulated number of the tokens of each channel, and rate adaptation of all the channels is achieved.

The invention relates to the technical field of electrical parameter measurement, and discloses a ring main unit multi-loop electrical parameter combined measurement and anomaly positioning method. The method is used for solving the problem that a unified time reference and channel-level synchronization mechanism is lacked in the collection process in a traditional method. The method comprises the following steps: firstly, by solidifying the configuration of a ring main unit loop and a sampling channel and generating a configuration verification identifier, establishing a main clock monotone increasing timing reference and consistently distributing a unified time mark number; a channel compensation gear is determined and solidified through calibration excitation, and a combined measurement frame with a data quality field is constructed and cached according to a time mark number in an operation period; after an event is triggered, according to an event starting point identifier and an event relative sequence number alignment frame segment, abnormal loop positioning information with an evidence range is output under consistency constraint and direction criteria, and cross-loop joint quantity stabilization and positioning result rechecking are achieved.

The invention discloses a laboratory constant-illumination-intensity sunlight illumination management system, belongs to the technical field of illumination management, and solves the problems that an ADC sampling clock of an irradiance feedback signal is modulated by switching noise and picosecond-level random jitter is generated, so that the phase collapse of a control loop is caused by ADC sampling jitter; and the problem that the service life of the lamp is shortened due to high-frequency self-oscillation caused by misjudgment of the phase of the digital PID controller and acceleration of lamp electrode sputtering is solved. According to the invention, an ultra-stable 156.25 MHz main clock signal is generated and is differentiated into four paths of 90-degree phase difference sampling clocks to drive a time-interleaved ADC array to execute anti-jitter four-phase sampling, clock jitter parameters are quantified in real time, a future jitter trend is predicted, and a compensation voltage is output to a phase modulation compensation module to generate an anti-phase correction signal to be injected into a compensation node of a clock distribution network; and finally, the digital correction engine executes complex exponential weighted average and finite impulse response filtering processing on the four-channel sampling data, outputs a control signal with small fluctuation, and recovers the service life of the xenon lamp.

The present application relates to the technical field of optical fiber Ethernet clock synchronization, in particular to a kind of optical fiber Ethernet multi-node clock synchronization control method and system.For the frame start delimiter in multistage optical fiber Ethernet link is transferred to the position deviating from the predetermined count position after reaching, the number of idle code groups under different port clock domain is not easy to match, main clock node sends reserved idle code group before synchronization frame and issues periodic serial number, main clock sends count value and the predetermined count position of each level node, relay node detects frame start delimiter and then latches arrival count value, determines the number of idle code groups to be increased or to be reduced according to difference value and the count length corresponding to single idle code group, adjusts the number of idle code groups before synchronization frame before forwarding, and the slave node determines output count position and generates second pulse or sampling trigger signal accordingly, thereby improving the consistency of multi-node synchronization output.

This invention relates to the field of signal processing technology and discloses a clock control system and method. In this invention, the first clock module and the second clock module have the same structure. The input terminal of a phase detector is connected to both the first and second clock modules, and the output terminal is connected to a controller. The phase detector compares and determines the phase difference between the clock signals output by the first and second clock modules and feeds it back to the controller. The controller is connected to both the first and second clock modules and outputs an adjustment signal to either the first or second clock module based on the phase difference. A combiner is connected to both the first and second clock modules and combines the clock signals output by the first and second clock modules before outputting the result. Self-calibration is achieved through the main clock link and the compensation clock link, reducing the phase difference between the clock signals of the main clock link and the compensation clock link, eliminating interference from the external environment, thereby reducing phase noise and improving stability.

A communication circuit with reduced kickback noise of an eye opening monitor may include a first sampler, a second sampler, and a preamplifier, wherein when an edge of a sub-clock precedes an edge of a main clock, the first sampler samples a data value by comparing the input signal with a second reference voltage at the edge of the sub-clock, and the second sampler samples a data value by comparing the input signal with a first reference voltage at the edge of the main clock, and when the edge of the sub-clock lags the edge of the main clock, the second sampler samples a data value by comparing the input signal with the second reference voltage at the edge of the sub-clock, and the first sampler samples a data value by comparing the input signal with the first reference voltage at the edge of the main clock.

Embodiments of the present application provide a chip layout and wiring method, device, computer equipment and readable storage medium, the method comprises: according to the preset prevention voltage drop cell attribute information, determine a plurality of to be encrypted units, wherein the prevention voltage drop cell attribute information includes at least one of the following: the cell type is main clock gating, the fanout of the cell is greater than the preset fanout value, the drive of the cell is greater than the preset drive value;The position of each to-be-encrypted unit is determined respectively;According to the position of each to-be-encrypted unit, the bottom Powermesh of the plurality of to-be-encrypted units is encrypted to obtain the encrypted position of each to-be-encrypted unit. Through the method, the problem of voltage drop can be solved in advance, and the problems of affecting timing and low efficiency caused by solving the problem of voltage drop after the layout and wiring stage can be avoided.

The application provides a method for improving PWM resolution, adopts a lookup table method to realize resolution PWM adjustment output, and the resolution is less than 0.1%. In the looked-up table, the full sequence of frequency division coefficients is arranged in a cycle with the frequency division coefficient sub-sequence as a period, and the frequency division coefficient sub-sequence adopts a first arithmetic sequence. The full sequence of high level is composed of multiple different high level sub-sequences, all high level values in the same high level sub-sequence are the same, and the values form a second arithmetic sequence with the values of the adjacent high level sub-sequences. Each frequency division coefficient sub-sequence corresponds to a high level sub-sequence. The increasing and decreasing change directions of the above-mentioned first arithmetic sequence and the second arithmetic sequence are opposite. The application improves the resolution of PWM without improving the frequency of the main clock, the output is stable, the MCU occupation is low, and the application is simple, convenient and easy to use. Without reducing the output frequency of PWM, the energy storage inductance and filter capacitance are reduced, and the circuit board area is reduced.

The embodiment of the invention relates to the technical field of vehicles, and discloses a vehicle end time service method and device and a vehicle, and the method comprises the steps: judging whether the time difference between a standby clock source and a main clock source is within a preset range or not when the vehicle is switched from the standby clock source to the main clock source; if yes, switching to the master clock source as a system time source for timing, and outputting a timestamp message according to the master clock source; if not, the standby clock source serves as a system time source for timing, and timestamp messages output according to the standby clock source are accumulated or subtracted according to a preset step length, so that the timestamp messages are gradually close to the time of the main clock source until the time difference between the timestamp messages obtained through accumulation and the main clock source is within a preset range, and the time difference between the timestamp messages obtained through accumulation and the time difference between the timestamp messages obtained through accumulation and the time difference between the timestamp messages obtained through accumulation and the main clock source is within the preset range; the standby clock source comprises an RTC time component or an NTP time component, and the main clock source comprises a GNSS module. By applying the technical scheme of the invention, the problem of log function loss caused by time jump in the prior art can be solved.

The utility model relates to a clock synchronization phase-locked loop based on a fractional order filter. The clock synchronization phase-locked loop comprises a phase frequency detector, a charge pump, a loop order filter and a voltage-controlled oscillator. The phase frequency detector comprises a main clock input end and a local clock input end; the charge pump is electrically connected between the output end of the phase frequency detector and the input end of the loop order filter; the loop order filter is a fractional order filter and comprises an equivalent fractional order capacitor filter circuit and an RC filter circuit which are arranged in parallel; the output end of the loop order filter is electrically connected to the input end of the voltage-controlled oscillator; the output end of the voltage-controlled oscillator outputs a local clock and is electrically connected to the local clock input end of the phase frequency detector. According to the utility model, the circuit realization problem of the fractional order filter is solved, and the performance and the stability of the phase-locked loop are improved based on the construction of the equivalent fractional order capacitor filter circuit.

Embodiments of the present application disclose a clock synchronization method and a vehicle-mounted device. The method is applied to the vehicle-mounted device, and the vehicle-mounted device comprises a first communication module for acquiring system messages, a second communication module for acquiring satellite navigation signals, a vehicle-mounted main clock module and a reference clock module. The method comprises: if the satellite navigation signals cannot be acquired, the first communication module performs clock synchronization on the vehicle-mounted main clock module according to the system messages; if the system messages cannot be acquired, the second communication module performs clock synchronization on the vehicle-mounted main clock module according to the satellite navigation signals; and if the system messages cannot be acquired and the satellite navigation signals cannot be acquired, the vehicle-mounted main clock module performs counting according to signals provided by the reference clock module to perform clock synchronization, so that the vehicle-mounted main clock module is clock-synchronized in a joint manner of the first communication module, the second communication module and the reference clock module.

The application discloses a clock tree structure and an implementation method thereof, and relates to the technical field of clock trees.The clock tree structure comprises a trunk clock network and a branch clock network.The trunk clock network is introduced from outside and is composed of a first-stage buffer unit and a second-stage buffer unit.The trunk can be horizontal or vertical.The branch clock network is introduced from the trunk clock network and is composed of a second-stage buffer unit to a third-stage buffer unit.The branch clock drives the load in a window with an L*L size, that is, the third-stage buffer unit drives a fourth-stage buffer unit in a tree structure, and so on, to drive an nth-stage buffer unit and a gated clock unit.The beneficial effects are as follows: the clock tree structure is built by establishing the trunk clock network and the branch clock network, the number of buffer units on the clock network is reduced, and the chip power consumption is reduced;the main clock tree and the sub clock network play the role of a common path, the number of stages of the clock tree is reduced, the influence of OCV on the clock is reduced, and the final timing convergence is easy.

The invention provides a time difference monoclinic ADC (Analog to Digital Converter) circuit, which comprises a ramp generator connected with a comparator, a time-to-digital converter, a latch and a parallel-serial conversion circuit which are cascaded at the rear end; the two phase-locked loops are connected with the time-to-digital converter, one phase-locked loop is used for providing a main clock for the time-to-digital converter, and the other phase-locked loop is used for providing a control voltage for the time-to-digital converter; and performing error quantization on the double-clock deviation between the clock output by the time-to-digital converter and the main clock through a vernier caliper quantization method so as to perform linearity calibration on the ADC circuit. According to the invention, aiming at the scene of applying the time interpolation monoclinic ADC, the deviation of the double clocks is accurately quantified through a vernier caliper quantization method, and the linearity of the monoclinic analog-to-digital converter is effectively improved.

The embodiment of the invention provides a vibration analysis system, and relates to the technical field of testing. The vibration analysis system comprises an upper computer and a data acquisition device, and in the data acquisition device, a main clock module is used for providing clock signals for each module; the rotating speed signal acquisition module is used for receiving a rotating speed coding signal of rotating equipment acquired by an encoder and processing the rotating speed coding signal to obtain a rotating speed digital signal; the vibration signal acquisition module is used for receiving a vibration sensing signal, acquired by a vibration sensor, of the rotating equipment and converting the vibration sensing signal into a vibration digital signal; the core processing module obtains an angle domain signal of the vibration digital signal according to the rotating speed digital signal and the vibration digital signal corresponding in time; and the upper computer is used for carrying out fault diagnosis on the rotating equipment based on the angle domain signal of the vibration of the rotating equipment. According to the invention, the synchronization precision of the rotating speed signal and the vibration signal is improved, and real-time fault diagnosis with higher precision can be realized.

The invention provides a distributed simulation system synchronization method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining a network message sent by other subsystems in a distributed simulation system through a subsystem, carrying out the recognition of the network message, obtaining a PTP message, and recording a first timestamp at which the PTP message arrives; calculating a first time deviation value and a first time delay value of the sub-clock node and the main clock node through the main controller according to the first timestamp; when the PTP message is sent to the switch, the residence time of the PTP message is calculated through the time residence bridge, and the residence time comprises a second time deviation value and a second delay value; and synchronizing the main clock node and the sub-clock node according to the residence time. The method has the beneficial effect that the accuracy and reliability of time synchronization of the distributed simulation system are improved.

The application relates to the technical field of vehicle-mounted combined navigation, in particular to a 5G communication double-clock source fused IMU error correction method and system; the method comprises the following steps: collecting GNSS main clock signals, auxiliary clock signals and 5G communication clock signals and establishing a unified time reference system; a lateral velocity prediction model is constructed to predict the lateral motion trajectory of a vehicle in a high-speed lane-changing process, the lateral motion trajectory is combined with IMU inertial measurement data to calculate the lateral offset residual error of the vehicle; the lateral offset residual error of the vehicle, the lane center line offset, the steering wheel turning angle data and the yaw rate data are input into an improved error risk prediction neural network model for joint processing; and an extended Kalman filter is used to correct the vehicle navigation state data in real time. The application realizes the high-precision IMU error correction of vehicle lane-changing navigation state correction by fusing 5G communication and GNSS double-clock sources in the vehicle high-speed lane-changing scene.