Fishbone-shaped clock tree and implementation method

Abstract

The invention belongs to the technical field of clock trees, and discloses a fishbone-shaped clock tree and an implementation method. The fishbone-shaped clock tree comprises: a main clock tree and a plurality of sub-clock trees, wherein the main clock tree is led out from a PLL, the sub-clock trees are led out from the main clock tree, and each sub-clock tree is provided with a plurality of clock branch points; each clock branch point is used as a source of a traditional clock tree to establish the traditional clock tree. The fishbone-shaped clock tree and the implementation method have the beneficial effects that a fishbone-shaped clock tree structure is established by establishing the main clock tree and the sub-clock trees, so that buffer units between a PLL and a chip sub-module are reduced, and the power consumption of chips is reduced; in addition, the main clock tree and the sub-clock trees also play a role of a common path, the OCV occupies a few clock cycles, and the final time sequence convergence is easy.

Description

technical field [0001] The invention relates to the technical field of clock trees, in particular to a fishbone clock tree and an implementation method. Background technique [0002] The clock tree is a network structure built in balance by many buffer units (buffer / inv cells). It has a source point, which is usually the clock input port (clock input port), or it may be a certain unit output pin (cell output pin), which is built by level-by-level buffer units. The key factors to measure the quality of the clock tree include: clock tree length, clock tree common path, clock tree signal transition time (clock transition time), clock tree drift (clock skew), clock tree noise, clock duty cycle. [0003] The clock tree construction scheme is a very important step in the physical design and implementation of the chip backend. The quality of the clock tree is directly related to the power consumption of the chip and the running speed of the chip. High-computing chips pursue extre...

AI Technical Summary

Problems solved by technology

[0005] Those skilled in the art know that too many clock buffers will cause the length of the clock tree to be long, the power consumption of the clock tree will be large, and it will easily cause channel wiring congestion, the clock tree wiring will take up more resources, and the noise on the clock tree will be large. Too many will also cause the clock tree to bifurcate early and the common path will be less, and the clock cycle occupied by OCV will be more, and the final timing convergence will be difficult

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