Pipelined analog-to-digital converter (ADC) capable of carrying out background digital calibration

Abstract

The invention discloses a pipelined analog-digital converter (ADC) capable of carrying out background digital calibration. The pipelined (ADC) comprises a sampling hold circuit, M calibrated level circuit modules, N level circuit modules and a back level analog-to-digital conversion module which are sequentially connected in series, wherein each calibrated level circuit module is connected with a corresponding digital calibrated level circuit; the quantized value output port of the level circuit module and the quantized value output port of a back level analog-to-digital conversion module are respectively connected with a time delay and dislocation summation module; and the output end of the time delay and dislocation summation module is sequentially and reversely connected in series in the digital calibrated level circuit. The pipelined analog-to-digital converter provided by the invention has the advantages that the thinking is inventive, the analog circuit has a simple structure, a pseudo random number generator and a multi-way selection switch are additionally arranged on the foundation of the existing technical structure, and the working of other analog circuits can not be unaffected in the working process; and simultaneously, the principle of the digital circuit segment is simple and is easy to realize, the error of the pipelined ADC can be reduced obviously, the linearity of the pipelined ADC can be improved, and the dynamic properties of the pipelined ADC can be improved.

Description

technical field [0001] The invention relates to a pipelined analog-to-digital converter, in particular to a pipelined analog-to-digital converter which utilizes first-order and third-order errors for background digital calibration. Background technique [0002] Pipelined analog-to-digital converter (pipelined analog-to-digital converter, hereinafter referred to as pipelined ADC) is an important component commonly used in video image systems, digital subscriber loops, Ethernet transceivers, or wireless communication systems; Pipelined analog-to-digital conversion (A / D conversion, hereinafter referred to as A / D conversion) can achieve a good balance in power, speed, and integrated circuit chip area, so it can be used to achieve high-precision sampling frequency at the megahertz level ADC operation is in progress. [0003] Such as figure 1 Shown is a block diagram of a traditional pipeline ADC structure. After the analog signal passes through the sample-and-hold circuit 100, ...

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Problems solved by technology

[0007] However, in actual situations, there is a mismatch between the first capacitor 211 and the second capacitor 212, and the switch S1 and the switch S2 are nonlinear, and the operational amplifier 251 is not ideal (that is, the open-loop gain is limited and nonlinear), These non-ideal factors will cause the deterioration of the transfer curve. The actual margin transfer curve and the full transfer curve are shown as the solid lines in Fig. 4(a) and Fig. 4(b). This situation will make the ADC performance worse Difference

[0008] The current calibration technology for capacitance error, operational amplifier gain error and nonlinear error, the general analog circuit is more complicated, and the digital algorithm is more difficult to implement

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