Inter-process communication method and device

Abstract

An embodiment of the invention provides an inter-process communication method and device. The inter-process communication method includes establishing a first mapping relation between a shared memory address and a preset address of a first process, with the shared memory being obtained by applying by the first process; saving the first mapping relation to a TLB (translation lookside buffer) and a first page table corresponding to the first process, and locking the first mapping relation; controlling the first process to send mapping information containing the shared memory address to a second process so as to establish a first mapping relation between the shared memory address and a preset address of the second process, then saving the second mapping relation to the TLB and a second page table corresponding to the second process, and locking the second mapping relation, with the preset address of the second process being equal to that of the first process. In this way, after the context of the process is switched by the operation system kernel, the virtual address still can be correctly translated as the physical address according to the locking mapping relations, and the communication is achieved with improved performance.

Description

technical field [0001] The present invention relates to the technical field of communication, in particular to an inter-process communication method and device. Background technique [0002] In virtual memory technology, the page table is stored in the main memory, and the cost of querying the page table is relatively high. In order to solve this problem, a special cache is also used in the virtual memory solution, that is, the translation detection buffer TLB (Translation lookaside buffer), some entries of the page table are saved in the TLB. After a virtual address is given, the processor first queries the TLB. If the page table entry corresponding to the virtual address is stored in the TLB (called a TLB hit), the memory physical address corresponding to the virtual address can be obtained directly from the TLB, and then The corresponding page can be read from the memory according to the physical address; if the page table entry corresponding to the virtual address is no...

AI Technical Summary

Problems solved by technology

Compared with the switched process, all the entries saved in the TLB are invalid, which leads to a high TLB missing rate of the switched process in the early stage of operation, requiring multiple accesses to the main memory page table, which increases the overhead of inter-process communication , reducing the efficiency of inter-process communication

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