Memory device and method for booting a system using non-volatile memory
A non-volatile memory technology, applied in static memory, read-only memory, information storage, etc., can solve problems such as failure to perform erasure operation successfully, memory block bit line leakage affecting memory block, bit line leakage, etc.
Active Publication Date: 2018-01-09
ELITE SEMICON MEMORY TECH INC
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Problems solved by technology
In this case, a full wipe operation cannot be successfully performed
For example, refer to figure 1 , if a memory block has completed the preprogramming (preprogramming) step (step 12), but failed to complete the over erase correction (Over EraseCorrection, OEC) step (step 16) when the power is interrupted, then due to the over erase phenomenon may Leakage of the bit line
When the system is powered on again, the bit line leakage caused by the memory block that failed the OEC step may affect the associated memory blocks sharing the same bit line
If the associated memory block is used to store the booting code, the system may not be able to read the booting code when the system executes the booting procedure after re-powering
This can result in long boot times, or, the system may fail to boot
Method used
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Embodiment Construction
[0033] figure 2 A block diagram of a memory device 200 incorporating an embodiment of the present invention is shown. refer to figure 2 , the memory device 200 includes a non-volatile memory element 202 , a state register bank 204 , an OR gate circuit 206 , a control unit 208 and a leakage current correction unit 210 . The leakage current correction unit 210 includes a first bias voltage generator 212 , a second bias voltage generator 214 and a re-erase unit 216 .
[0034] refer to figure 2 , the non-volatile memory device 202 includes N memory blocks [0] to memory blocks [N−1] for storing normal data or boot codes, wherein N is a positive integer. For example, in this embodiment, the memory cells in the memory block [0] are configured to store normal data, and the memory cells in the memory block [1] are configured to store boot codes. In addition, the memory cells in the memory block [0] and the memory cells in the memory block [1] are electrically connected to the sa...
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A memory device and a method for booting a system using a non-volatile memory. A memory device according to an embodiment of the present invention includes a non-volatile memory element, a status register, a control unit and a leakage current correction unit. The non-volatile memory device includes a boot block and a plurality of data blocks, wherein the memory cells in the boot block and the memory cells in the data blocks are electrically connected to the same bit line. The status register is electrically connected to the non-volatile memory element and is configured to store a status flag for indicating whether a complete erase operation applied to the non-volatile memory element has been completed. The control unit is configured to read the flag value of the status flag after the memory device is powered on. The leakage current correction unit is electrically connected to the control unit, and is configured to selectively execute a leakage current suppression program on the non-volatile memory element according to the flag value of the state flag.
Description
technical field [0001] The present invention relates to a memory device; in particular, to a method for booting a system using a non-volatile memory element and a related memory device. Background technique [0002] In the process of erasing a non-volatile memory, and more specifically, in the process of erasing a particular block within a non-volatile memory, unexpected interruptions, such as unexpected power interruptions, may occur . In this case, a full wipe operation cannot be successfully performed. For example, refer to figure 1 , if a memory block has completed the preprogramming (preprogramming) step (step 12), but failed to complete the over erase correction (Over EraseCorrection, OEC) step (step 16) when the power is interrupted, then due to the over erase phenomenon may causing leakage on the bit line. When the system is powered on again, the bit line leakage caused by the memory block that failed the OEC step may affect the associated memory blocks sharing t...
Claims
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IPC IPC(8): G11C16/14G11C16/06
Inventor 郭忠山陈致豪
Owner ELITE SEMICON MEMORY TECH INC