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Multi-interface mode realization method of 1553B bus protocol IP (Internet Protocol) core

A technology of bus protocol and implementation method, which is applied in the direction of instruments, electrical digital data processing, etc., can solve the problems of poor scalability and single interface form, and achieve the effect of improving scalability

Active Publication Date: 2015-06-03
SHENZHEN STATE MICROELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] The purpose of the embodiments of the present invention is to provide a multi-interface mode implementation method of the 1553B bus protocol IP core, which aims to solve the problem that the existing 1553B bus protocol IP core has a single interface form and can only be matched with the read-write control mode. The problem of poor scalability for data transmission

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  • Multi-interface mode realization method of 1553B bus protocol IP (Internet Protocol) core
  • Multi-interface mode realization method of 1553B bus protocol IP (Internet Protocol) core
  • Multi-interface mode realization method of 1553B bus protocol IP (Internet Protocol) core

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Embodiment 1

[0031] Embodiment 1 of the present invention proposes a method for implementing a multi-interface mode of a 1553B bus protocol IP core, such as figure 2 shown, including:

[0032] Step S1: Obtain the first configuration instruction sent by the microprocessor through the interface unit, and identify the read / write control mode matching the microprocessor as transparent mode or buffer mode according to the first configuration instruction.

[0033] In Embodiment 1 of the present invention, the identification of the transparent mode or the buffer mode can be realized according to whether the first configuration command is at a high level or a low level. For example, if the first configuration command trans_buf is high level, that is, trans_buf=1, the read-write control mode can be recognized as transparent mode; if the first configuration command trans_buf is low level, that is, trans_buf=0, the read-write control mode can be recognized for buffer mode.

[0034] Step S2: If it ...

Embodiment 2

[0045] Embodiment 2 of the present invention proposes a multi-interface management system, such as image 3 As shown, for ease of description, only the part related to Embodiment 2 of the present invention is shown.

[0046] In detail, the multi-interface management system provided by Embodiment 2 of the present invention includes: a first identification module 11, configured to obtain the first configuration instruction sent by the microprocessor through the interface unit, and identify the interface that matches the microprocessor according to the first configuration instruction. The read-write control mode is a transparent mode or a buffer mode; the second identification module 12 is used to obtain the information sent by the microprocessor through the interface unit when the first identification module 11 identifies that the read-write control mode matched with the microprocessor is a transparent mode. According to the second configuration instruction, the read-write contr...

Embodiment 3

[0051] The third embodiment of the present invention proposes a 1553B bus protocol IP core, such as Figure 4 As shown, for ease of description, only the part related to Embodiment 3 of the present invention is shown.

[0052] In detail, the 1553B bus protocol IP core includes: an interface unit 22, the interface unit 22 is connected to the microprocessor through the data line C, the address line D, and the control line E, and can also be connected to an external memory according to actual needs; A shared memory 23 of 22; a protocol processing unit 24 connecting the interface unit 22 and the microprocessor; a protocol codec unit 25 connecting the protocol processing unit 24. Wherein, the internal structure and function of the protocol processing unit 24 are as follows: figure 1 shown, and will not be described here.

[0053] Different from the existing 1553B bus protocol IP core, the 1553B bus protocol IP core also includes a multi-interface management system 21 connected to...

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Abstract

The invention belongs to the field of the IP (Internet Protocol) core design of a 1553B bus protocol, and provides a multi-interface mode realization method of a 1553B bus protocol IP core. The method receives and identifies a relevant configuration command of a microprocessor to realize the identification of a read-write control mode of an interface unit in the 1553B bus protocol IP core. The multi-interface mode realization method can identify two read-write control modes including an external memory used for reading and writing the inside of the 1553B bus protocol IP core and a shared memory used for reading and writing the 1553B bus protocol IP core under a transparent mode, can identify a 16-bit non zero latency buffer mode and a 16-bit zero latency buffer mode under a buffer mode and also can identity a 8-bit non zero latency buffer mode and a 8-bit zero latency buffer mode under the buffer mode so as to solve the problem of single interface mode of the traditional 1553B bus protocol IP core and improve expandability.

Description

technical field [0001] The invention belongs to the field of IP core design based on the 1553B bus protocol, and in particular relates to a multi-interface mode realization method of the 1553B bus protocol IP core. Background technique [0002] 1553B bus protocol, also known as MIL-STD-1553B bus interface protocol. It is known that the transmission rate of the 1553B bus is 1 Mbps, the transmission protocol is a command / response mode, the transmission medium is a shielded twisted pair, and the fault tolerance mechanism is a typical dual redundancy mode. The devices hanging on the 1553B bus are terminal devices, and the terminal devices include three types: Bus Controller (Bus Controller, BC), which is used as the controller and manager of the bus; Remote Terminal (RT), which uses Obtain effective commands from the bus and make a response to complete the corresponding actions; the bus monitor (Monitor Terminal, MT) is used to monitor and record data on the bus. The 1553B bus...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/38
CPCG06F13/387G06F13/4027G06F2213/0012
Inventor 安晓鹏张京周锦刘云龙
Owner SHENZHEN STATE MICROELECTRONICS CO LTD
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