Manufacturing method of memory

Abstract

A method of manufacturing a memory, including providing a substrate, which includes a memory cell region and a peripheral region; forming a plurality of first gates on the memory cell region and at least one second gate on the peripheral region; forming a sacrificial electrode on the substrate layer; forming a first stop layer on the sacrificial layer of the memory cell region; performing an etching process using the first stop layer as a mask; compliantly forming a second stop layer on the substrate; depositing a dielectric material on the second stop layer ; Using the first and second stop layers on the memory cell region as grinding stop layers to perform a planarization process on the dielectric material; removing the first stop layer and the second stop layer on the memory cell region; and removing the first After the stop layer and the second stop layer, the sacrificial layer on the memory cell region is removed to form a plurality of first contact openings between the first gate electrodes. The present invention forms stop layers of different thicknesses on the memory cell area and the peripheral area, so that the landing area of ​​the contact plug will not be compressed when the size of the memory is further reduced.

Description

technical field [0001] The invention relates to a manufacturing method of a memory. Background technique [0002] Generally speaking, as the size of the memory gradually shrinks, in order to overcome the increasingly smaller line width and prevent misalignment of the contact plugs, self-aligned contact plugs (self-aligned contacts, SAC) will be used. craft. [0003] In the self-aligned contact plug process, the thickness of the sidewall of the gate affects the size of the contact plug formed between the gates. The memory device includes a memory cell area and a peripheral area. Generally speaking, gates are formed in the memory cell area and the peripheral area at the same time. Afterwards, an etching process is performed on the sidewall of the gate to facilitate subsequent formation of contact plugs. [0004] However, in some memory structures, metal silicides are formed on the gate, source, and drain regions in the peripheral region. If the etching process is performed...

AI Technical Summary

Problems solved by technology

If the sidewall of the gate is etched, the metal silicide will be exposed, which will affect the electrical characteristics of the memory

Therefore, in the memory structure with metal silicide formed on the gate and source / drain regions of the peripheral region, the spacer (sidewall) of the gate cannot be etched, which affects the formation of subsequent contact plugs

Therefore, when the size of the memory is further reduced, there will be a problem that the landing area of ​​the contact plug is compressed.

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